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Searched refs:E1000_PHY_CTRL (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/netif/ig_hal/
HDe1000_regs.h110 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ macro
111 #define E1000_POEMB E1000_PHY_CTRL /* PHY OEM Bits */
HDe1000_ich8lan.c2547 mac_reg = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_oem_bits_config_ich8lan()
3223 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_set_d0_lplu_state_ich8lan()
3227 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state_ich8lan()
3252 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state_ich8lan()
3316 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_set_d3_lplu_state_ich8lan()
3320 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state_ich8lan()
3361 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state_ich8lan()
5492 phy_ctrl = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_kmrn_lock_loss_workaround_ich8lan()
5495 E1000_WRITE_REG(hw, E1000_PHY_CTRL, phy_ctrl); in e1000_kmrn_lock_loss_workaround_ich8lan()
5555 reg = E1000_READ_REG(hw, E1000_PHY_CTRL); in e1000_igp3_phy_powerdown_workaround_ich8lan()
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HDe1000_phy.c3447 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) in e1000_access_phy_wakeup_reg_bm()
/dragonfly/sys/dev/netif/igb/
HDif_igb.c5114 DUMPREG(E1000_PHY_CTRL); in igb_reg_dump()