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Searched refs:GEN7_MISCCPCTL (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/i915/
HDintel_guc_fw.c212 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE | in guc_ucode_xfer()
213 I915_READ(GEN7_MISCCPCTL))); in guc_ucode_xfer()
HDi915_perf.c1357 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1397 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) |
HDintel_engine_cs.c1220 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & in bxt_init_workarounds()
HDi915_irq.c1283 misccpctl = I915_READ(GEN7_MISCCPCTL); in ivybridge_parity_work()
1284 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); in ivybridge_parity_work()
1285 POSTING_READ(GEN7_MISCCPCTL); in ivybridge_parity_work()
1325 I915_WRITE(GEN7_MISCCPCTL, misccpctl); in ivybridge_parity_work()
HDi915_drv.c2280 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2362 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
HDintel_pm.c96 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) in gen9_init_clock_gating()
8488 misccpctl = I915_READ(GEN7_MISCCPCTL); in gen8_set_l3sqc_credits()
8489 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); in gen8_set_l3sqc_credits()
8503 I915_WRITE(GEN7_MISCCPCTL, misccpctl); in gen8_set_l3sqc_credits()
HDi915_reg.h8053 #define GEN7_MISCCPCTL _MMIO(0x9424) macro