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Searched refs:PA_CL_ENHANCE (Results 1 – 16 of 16) sorted by relevance

/dragonfly/sys/dev/drm/radeon/reg_srcs/
HDevergreen24 0x00008A14 PA_CL_ENHANCE
HDcayman23 0x00008A14 PA_CL_ENHANCE
HDr60053 0x00008A14 PA_CL_ENHANCE
/dragonfly/sys/dev/drm/radeon/
HDrv770d.h482 #define PA_CL_ENHANCE 0x8A14 macro
HDnid.h357 #define PA_CL_ENHANCE 0x8A14 macro
HDsid.h1082 #define PA_CL_ENHANCE 0x8A14 macro
HDcikd.h1143 #define PA_CL_ENHANCE 0x8A14 macro
HDrv770.c1594 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | in rv770_gpu_init()
HDevergreend.h977 #define PA_CL_ENHANCE 0x8A14 macro
HDni.c1256 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); in cayman_gpu_init()
HDr600d.h374 #define PA_CL_ENHANCE 0x8A14 macro
HDsi.c3340 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); in si_gpu_init()
4423 case PA_CL_ENHANCE: in si_vm_reg_valid()
HDevergreen_cs.c3253 case PA_CL_ENHANCE: in evergreen_vm_reg_valid()
HDr600.c2376 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | in r600_gpu_init()
HDevergreen.c3685 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); in evergreen_gpu_init()
HDcik.c3442 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); in cik_gpu_init()