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Searched refs:SCLK_MUX_SEL_MASK (Results 1 – 16 of 16) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
HDrv740d.h36 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
HDrv730d.h39 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
HDrv740_dpm.c152 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in rv740_populate_sclk_value()
371 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in rv740_populate_smc_acpi_state()
HDrv730_dpm.c84 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in rv730_populate_sclk_value()
294 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in rv730_populate_smc_acpi_state()
HDrv770d.h102 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
HDnid.h549 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
HDsid.h96 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
HDcikd.h259 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
HDrv770_dpm.c535 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in rv770_populate_sclk_value()
983 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in rv770_populate_smc_acpi_state()
HDrv770.c1139 tmp &= SCLK_MUX_SEL_MASK; in rv770_set_clk_bypass_mode()
HDevergreend.h84 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
HDni_dpm.c1900 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in ni_populate_smc_acpi_state()
2031 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in ni_calculate_sclk_params()
HDcypress_dpm.c1430 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in cypress_populate_smc_acpi_state()
HDsi_dpm.c4574 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in si_populate_smc_acpi_state()
4814 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in si_calculate_sclk_params()
HDci_dpm.c3059 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in ci_populate_smc_acpi_level()
/dragonfly/sys/dev/drm/amd/amdgpu/
HDsi_dpm.c5038 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in si_populate_smc_acpi_state()
5277 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in si_calculate_sclk_params()