Searched refs:SCL_MODE (Results 1 – 5 of 5) sorted by relevance
| /dragonfly/sys/dev/drm/amd/display/dc/dce/ |
| HD | dce_transform.c | 125 REG_UPDATE_2(SCL_MODE, SCL_MODE, 0, SCL_PSCL_EN, 0); in setup_scaling_configuration()
127 REG_UPDATE(SCL_MODE, SCL_MODE, 0); in setup_scaling_configuration()
136 REG_UPDATE(SCL_MODE, SCL_MODE, 1); in setup_scaling_configuration()
138 REG_UPDATE(SCL_MODE, SCL_MODE, 2); in setup_scaling_configuration()
141 REG_UPDATE(SCL_MODE, SCL_PSCL_EN, 1); in setup_scaling_configuration()
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| HD | dce_transform.h | 76 SRI(SCL_MODE, SCL, id), \
159 XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \
205 XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh)
252 XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \
341 type SCL_MODE; \
424 uint32_t SCL_MODE; member
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| /dragonfly/sys/dev/drm/amd/display/dc/dcn10/ |
| HD | dcn10_dpp_dscl.c | 348 uint32_t scl_mode = REG_READ(SCL_MODE); in dpp1_dscl_set_scl_filter()
382 REG_SET_2(SCL_MODE, scl_mode, in dpp1_dscl_set_scl_filter()
539 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);
695 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode); in dpp1_dscl_set_scaler_manual_scale()
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| HD | dcn10_dpp.h | 56 SRI(SCL_MODE, DSCL, id), \
1099 uint32_t SCL_MODE; \
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| /dragonfly/sys/dev/drm/amd/display/dc/dce110/ |
| HD | dce110_transform_v.c | 177 set_reg_field_value(value, 1, SCLV_MODE, SCL_MODE); in setup_scaling_configuration()
181 set_reg_field_value(value, 0, SCLV_MODE, SCL_MODE); in setup_scaling_configuration()
192 get_reg_field_value(value, SCLV_MODE, SCL_MODE), in setup_scaling_configuration()
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