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Searched refs:SR (Results 1 – 25 of 45) sorted by relevance

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/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
HDdcn10_hubbub.h33 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\
34 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\
35 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\
36 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\
37 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\
38 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\
39 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\
40 SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\
41 SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\
42 SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\
[all …]
/dragonfly/sys/dev/drm/amd/display/dc/dce/
HDdce_dmcu.h33 SR(DMCU_CTRL), \
34 SR(DMCU_STATUS), \
35 SR(DMCU_RAM_ACCESS_CTRL), \
36 SR(DMCU_IRAM_WR_CTRL), \
37 SR(DMCU_IRAM_WR_DATA), \
38 SR(MASTER_COMM_DATA_REG1), \
39 SR(MASTER_COMM_DATA_REG2), \
40 SR(MASTER_COMM_DATA_REG3), \
41 SR(MASTER_COMM_CMD_REG), \
42 SR(MASTER_COMM_CNTL_REG), \
[all …]
HDdce_hwseq.h31 SR(LVTMA_PWRSEQ_CNTL), \
32 SR(LVTMA_PWRSEQ_STATE)
49 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
82 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
83 SR(DCFEV_CLOCK_CONTROL), \
92 SR(BLNDV_CONTROL),\
130 SR(DCHUB_FB_LOCATION),\
131 SR(DCHUB_AGP_BASE),\
132 SR(DCHUB_AGP_BOT),\
133 SR(DCHUB_AGP_TOP), \
[all …]
HDdce_abm.h33 SR(BL_PWM_PERIOD_CNTL), \
34 SR(BL_PWM_CNTL), \
35 SR(BL_PWM_CNTL2), \
36 SR(BL_PWM_GRP1_REG_LOCK), \
37 SR(LVTMA_PWRSEQ_REF_DIV), \
38 SR(MASTER_COMM_CNTL_REG), \
39 SR(MASTER_COMM_CMD_REG), \
40 SR(MASTER_COMM_DATA_REG1)
44 SR(DC_ABM1_HG_SAMPLE_RATE), \
45 SR(DC_ABM1_LS_SAMPLE_RATE), \
[all …]
HDdce_audio.h33 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\
34 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\
35 SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\
36 SR(DCCG_AUDIO_DTO_SOURCE),\
37 SR(DCCG_AUDIO_DTO0_MODULE),\
38 SR(DCCG_AUDIO_DTO0_PHASE),\
39 SR(DCCG_AUDIO_DTO1_MODULE),\
40 SR(DCCG_AUDIO_DTO1_PHASE)
HDdce_link_encoder.h47 SR(DMCU_RAM_ACCESS_CTRL), \
48 SR(DMCU_IRAM_RD_CTRL), \
49 SR(DMCU_IRAM_RD_DATA), \
50 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
76 SR(DCI_MEM_PWR_STATUS)
86 SR(DCI_MEM_PWR_STATUS)
93 SR(DCI_MEM_PWR_STATUS)
99 SR(DCI_MEM_PWR_STATUS)
HDdce_aux.h37 SR(AUXN_IMPCAL), \
38 SR(AUXP_IMPCAL)
HDdce_mem_input.h79 SR(DCHUB_FB_LOCATION),\
80 SR(DCHUB_AGP_BASE),\
81 SR(DCHUB_AGP_BOT),\
82 SR(DCHUB_AGP_TOP)
HDdce_clocks.h37 SR(DENTIST_DISPCLK_CNTL)
/dragonfly/sys/dev/drm/amd/display/dc/i2caux/dce110/
HDi2c_hw_engine_dce110.h32 SR(DC_I2C_ARBITRATION),\
33 SR(DC_I2C_CONTROL),\
34 SR(DC_I2C_SW_STATUS),\
35 SR(DC_I2C_TRANSACTION0),\
36 SR(DC_I2C_TRANSACTION1),\
37 SR(DC_I2C_TRANSACTION2),\
38 SR(DC_I2C_TRANSACTION3),\
39 SR(DC_I2C_DATA),\
40 SR(MICROSECOND_TIME_BASE_DIV)
HDaux_engine_dce110.h38 SR(AUXN_IMPCAL), \
39 SR(AUXP_IMPCAL)
HDi2caux_dce110.c158 #define SR(reg_name)\ macro
/dragonfly/sys/dev/netif/sbsh/
HDif_sbsh.c63 u_int8_t CR, CRB, SR, IMR, CTDR, LTDR, CRDR, LRDR; member
384 sc->regs->SR = 0xff; in init_card()
553 if (sc->regs->SR & TXS) { in sbsh_watchdog()
554 sc->regs->SR = TXS; in sbsh_watchdog()
566 u_int8_t status = sc->regs->SR; in sbsh_intr()
573 sc->regs->SR = EXT; in sbsh_intr()
578 sc->regs->SR = UFL; in sbsh_intr()
584 sc->regs->SR = RXS; in sbsh_intr()
590 sc->regs->SR = TXS; in sbsh_intr()
597 sc->regs->SR = CRC; in sbsh_intr()
[all …]
/dragonfly/contrib/ee/
HDnew_curse.c1497 Ntemp->SR = start_l;
2093 …columns=%d, lines=%d, SC=%d, SR=%d\n",window->Num_cols, window->Num_lines, window->SC, window->SR);
2148 if (window->SR >= virtual_scr->Num_lines)
2154 virtual_scr->LY = window->LY + window->SR;
2159 for (line_counter = 0; line_counter < window->SR; line_counter++)
2164 && ((line_counter + window->SR) < virtual_scr->Num_lines);
2981 for (i = 0, tmp = curscr->first_line; i < window->SR; i++)
2983 if ((end_row + window->SR) == 0)
3001 for (i = 0, tmp = curscr->first_line; (tmp->next_screen != NULL) && (i < window->SR); i++)
3011 if ((row + window->SR) == 0)
[all …]
HDnew_curse.h167 int SR; /* starting row */ member
/dragonfly/contrib/binutils-2.27/gas/doc/
HDc-msp430.texi53 Do not update the @code{SR} and the @code{PC} in the same instruction.
57 Do not use an arithmetic instruction to modify the @code{SR}.
83 SR}, @code{BIS #8, SR} or @code{MOV.W <>, SR}) must be
190 Register names @samp{PC}, @samp{SP} and @samp{SR} cannot be used as register names
HDc-sh.texi301 ldc Rn,SR mov.w @@Rm+,Rn
304 ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR)
314 or #imm,R0 stc.l SR,@@-Rn
336 stc SR,Rn
/dragonfly/sys/dev/drm/amd/display/dc/i2caux/dce100/
HDi2caux_dce100.c45 #define SR(reg_name)\ macro
/dragonfly/sys/dev/drm/amd/display/dc/i2caux/dce112/
HDi2caux_dce112.c46 #define SR(reg_name)\ macro
/dragonfly/sys/dev/drm/amd/display/dc/i2caux/dcn10/
HDi2caux_dcn10.c56 #define SR(reg_name)\ macro
/dragonfly/sys/dev/drm/amd/display/dc/i2caux/dce120/
HDi2caux_dce120.c56 #define SR(reg_name)\ macro
/dragonfly/contrib/gdb-7/gdb/stubs/
HDsh-stub.c265 R15, PC, PR, GBR, VBR, MACH, MACL, SR, enumerator
568 if (registers[SR] & T_BIT_MASK) in doSStep()
584 if (registers[SR] & T_BIT_MASK) in doSStep()
/dragonfly/initrd/etc/
HDtermcap14 :IC=\E[%d@:DC=\E[%dP:SF=\E[%dS:SR=\E[%dT:AL=\E[%dL:DL=\E[%dM:\
/dragonfly/sys/dev/drm/amd/display/dc/i2caux/dce80/
HDi2caux_dce80.c62 #define SR(reg_name)\ macro
/dragonfly/bin/mined/
HDmined1.c1609 case 'a':return(SR); in escfunc()
1616 case 'S': return(SR); in escfunc()
1635 case 'R': return(SR); /* shift-F3 */ in escfunc()

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