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Searched refs:VGA_HDP_CONTROL (Results 1 – 13 of 13) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
HDavivod.h53 #define VGA_HDP_CONTROL 0x328 macro
HDsid.h74 #define VGA_HDP_CONTROL 0x328 macro
HDcikd.h435 #define VGA_HDP_CONTROL 0x328 macro
HDevergreen.c2654 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); in evergreen_mc_stop()
2826 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); in evergreen_mc_resume()
2853 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in evergreen_mc_program()
HDrv770.c1025 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in rv770_mc_program()
HDr600.c1314 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in r600_mc_program()
HDsi.c4149 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in si_mc_program()
HDcik.c5327 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in cik_mc_program()
/dragonfly/sys/dev/drm/amd/amdgpu/
HDgmc_v9_0.c1093 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v9_0_hw_init()
HDgmc_v7_0.c277 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v7_0_mc_program()
HDgmc_v8_0.c468 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in gmc_v8_0_mc_program()
HDdce_v10_0.c437 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); in dce_v10_0_set_vga_render_state()
439 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in dce_v10_0_set_vga_render_state()
HDdce_v11_0.c453 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); in dce_v11_0_set_vga_render_state()
455 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); in dce_v11_0_set_vga_render_state()