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Searched refs:gart (Results 1 – 25 of 26) sorted by relevance

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/dragonfly/sys/dev/drm/radeon/
HDradeon_gart.c72 ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size, in radeon_gart_table_ram_alloc()
73 &rdev->gart.table_addr); in radeon_gart_table_ram_alloc()
81 rdev->gart.table_size >> PAGE_SHIFT); in radeon_gart_table_ram_alloc()
84 rdev->gart.ptr = ptr; in radeon_gart_table_ram_alloc()
85 memset((void *)rdev->gart.ptr, 0, rdev->gart.table_size); in radeon_gart_table_ram_alloc()
100 if (rdev->gart.ptr == NULL) { in radeon_gart_table_ram_free()
106 set_memory_wb((unsigned long)rdev->gart.ptr, in radeon_gart_table_ram_free()
107 rdev->gart.table_size >> PAGE_SHIFT); in radeon_gart_table_ram_free()
110 pci_free_consistent(rdev->pdev, rdev->gart.table_size, in radeon_gart_table_ram_free()
111 (void *)rdev->gart.ptr, in radeon_gart_table_ram_free()
[all …]
HDrs400.c78 if (rdev->gart.ptr) { in rs400_gart_init()
101 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rs400_gart_init()
159 tmp = (u32)rdev->gart.table_addr & 0xfffff000; in rs400_gart_enable()
160 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; in rs400_gart_enable()
187 (unsigned long long)rdev->gart.table_addr); in rs400_gart_enable()
188 rdev->gart.ready = true; in rs400_gart_enable()
231 u32 *gtt = rdev->gart.ptr; in rs400_gart_set_page()
HDradeon_asic.c167 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; in radeon_agp_disable()
168 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; in radeon_agp_disable()
169 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; in radeon_agp_disable()
173 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; in radeon_agp_disable()
174 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; in radeon_agp_disable()
175 rdev->asic->gart.set_page = &r100_pci_gart_set_page; in radeon_agp_disable()
209 .gart = {
277 .gart = {
373 .gart = {
441 .gart = {
[all …]
HDr300.c113 void __iomem *ptr = rdev->gart.ptr; in rv370_pcie_gart_set_page()
125 if (rdev->gart.robj) { in rv370_pcie_gart_init()
136 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rv370_pcie_gart_init()
137 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; in rv370_pcie_gart_init()
138 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; in rv370_pcie_gart_init()
139 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; in rv370_pcie_gart_init()
149 if (rdev->gart.robj == NULL) { in rv370_pcie_gart_enable()
164 table_addr = rdev->gart.table_addr; in rv370_pcie_gart_enable()
179 rdev->gart.ready = true; in rv370_pcie_gart_enable()
HDrs600.c537 if (rdev->gart.robj) { in rs600_gart_init()
546 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in rs600_gart_init()
555 if (rdev->gart.robj == NULL) { in rs600_gart_enable()
592 rdev->gart.table_addr); in rs600_gart_enable()
609 (unsigned long long)rdev->gart.table_addr); in rs600_gart_enable()
610 rdev->gart.ready = true; in rs600_gart_enable()
650 void __iomem *ptr = (void *)rdev->gart.ptr; in rs600_gart_set_page()
HDrv770.c895 if (rdev->gart.robj == NULL) { in rv770_pcie_gart_enable()
924 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in rv770_pcie_gart_enable()
935 (unsigned long long)rdev->gart.table_addr); in rv770_pcie_gart_enable()
936 rdev->gart.ready = true; in rv770_pcie_gart_enable()
HDr100.c639 if (rdev->gart.ptr) { in r100_pci_gart_init()
647 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in r100_pci_gart_init()
648 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; in r100_pci_gart_init()
649 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; in r100_pci_gart_init()
650 rdev->asic->gart.set_page = &r100_pci_gart_set_page; in r100_pci_gart_init()
665 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); in r100_pci_gart_enable()
671 (unsigned long long)rdev->gart.table_addr); in r100_pci_gart_enable()
672 rdev->gart.ready = true; in r100_pci_gart_enable()
695 u32 *gtt = rdev->gart.ptr; in r100_pci_gart_set_page()
HDradeon_ttm.c1157 if (p >= rdev->gart.num_cpu_pages) in radeon_ttm_gtt_read()
1160 page = rdev->gart.pages[p]; in radeon_ttm_gtt_read()
1166 kunmap(rdev->gart.pages[p]); in radeon_ttm_gtt_read()
HDni.c1287 if (rdev->gart.robj == NULL) { in cayman_pcie_gart_enable()
1316 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in cayman_pcie_gart_enable()
1362 (unsigned long long)rdev->gart.table_addr); in cayman_pcie_gart_enable()
1363 rdev->gart.ready = true; in cayman_pcie_gart_enable()
HDr600.c1072 void __iomem *ptr = (void *)rdev->gart.ptr; in r600_pcie_gart_tlb_flush()
1107 if (rdev->gart.robj) { in r600_pcie_gart_init()
1115 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in r600_pcie_gart_init()
1124 if (rdev->gart.robj == NULL) { in r600_pcie_gart_enable()
1161 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in r600_pcie_gart_enable()
1172 (unsigned long long)rdev->gart.table_addr); in r600_pcie_gart_enable()
1173 rdev->gart.ready = true; in r600_pcie_gart_enable()
HDradeon_vm.c368 uint64_t src = rdev->gart.table_addr + (addr >> 12) * 8; in radeon_vm_set_pages()
600 result = rdev->gart.pages_entry[addr >> RADEON_GPU_PAGE_SHIFT]; in radeon_vm_map_gart()
HDradeon.h1877 } gart; member
2378 struct radeon_gart gart; member
2730 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2731 #define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2732 #define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
HDevergreen.c2384 if (rdev->gart.robj == NULL) { in evergreen_pcie_gart_enable()
2422 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in evergreen_pcie_gart_enable()
2432 (unsigned long long)rdev->gart.table_addr); in evergreen_pcie_gart_enable()
2433 rdev->gart.ready = true; in evergreen_pcie_gart_enable()
HDsi.c4275 if (rdev->gart.robj == NULL) { in si_pcie_gart_enable()
4304 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in si_pcie_gart_enable()
4354 (unsigned long long)rdev->gart.table_addr); in si_pcie_gart_enable()
4355 rdev->gart.ready = true; in si_pcie_gart_enable()
/dragonfly/sys/dev/drm/amd/amdgpu/
HDamdgpu_gart.c115 if (adev->gart.robj == NULL) { in amdgpu_gart_table_vram_alloc()
119 bp.size = adev->gart.table_size; in amdgpu_gart_table_vram_alloc()
126 r = amdgpu_bo_create(adev, &bp, &adev->gart.robj); in amdgpu_gart_table_vram_alloc()
148 r = amdgpu_bo_reserve(adev->gart.robj, false); in amdgpu_gart_table_vram_pin()
151 r = amdgpu_bo_pin(adev->gart.robj, AMDGPU_GEM_DOMAIN_VRAM); in amdgpu_gart_table_vram_pin()
153 amdgpu_bo_unreserve(adev->gart.robj); in amdgpu_gart_table_vram_pin()
156 r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr); in amdgpu_gart_table_vram_pin()
158 amdgpu_bo_unpin(adev->gart.robj); in amdgpu_gart_table_vram_pin()
159 amdgpu_bo_unreserve(adev->gart.robj); in amdgpu_gart_table_vram_pin()
160 adev->gart.table_addr = amdgpu_bo_gpu_offset(adev->gart.robj); in amdgpu_gart_table_vram_pin()
[all …]
HDgmc_v7_0.c607 if (adev->gart.robj == NULL) { in gmc_v7_0_gart_enable()
645 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); in gmc_v7_0_gart_enable()
669 adev->gart.table_addr >> 12); in gmc_v7_0_gart_enable()
672 adev->gart.table_addr >> 12); in gmc_v7_0_gart_enable()
699 (unsigned long long)adev->gart.table_addr); in gmc_v7_0_gart_enable()
700 adev->gart.ready = true; in gmc_v7_0_gart_enable()
708 if (adev->gart.robj) { in gmc_v7_0_gart_init()
716 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v7_0_gart_init()
717 adev->gart.gart_pte_flags = 0; in gmc_v7_0_gart_init()
HDgmc_v9_0.c784 if (adev->gart.robj) { in gmc_v9_0_gart_init()
792 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v9_0_gart_init()
793 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE(MTYPE_UC) | in gmc_v9_0_gart_init()
1031 if (adev->gart.robj == NULL) { in gmc_v9_0_gart_enable()
1078 (unsigned long long)adev->gart.table_addr); in gmc_v9_0_gart_enable()
1079 adev->gart.ready = true; in gmc_v9_0_gart_enable()
HDgmc_v8_0.c834 if (adev->gart.robj == NULL) { in gmc_v8_0_gart_enable()
888 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); in gmc_v8_0_gart_enable()
912 adev->gart.table_addr >> 12); in gmc_v8_0_gart_enable()
915 adev->gart.table_addr >> 12); in gmc_v8_0_gart_enable()
943 (unsigned long long)adev->gart.table_addr); in gmc_v8_0_gart_enable()
944 adev->gart.ready = true; in gmc_v8_0_gart_enable()
952 if (adev->gart.robj) { in gmc_v8_0_gart_init()
960 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v8_0_gart_init()
961 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE; in gmc_v8_0_gart_init()
HDgfxhub_v1_0.c42 BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); in gfxhub_v1_0_init_gart_pt_regs()
43 value = adev->gart.table_addr - adev->gmc.vram_start in gfxhub_v1_0_init_gart_pt_regs()
HDamdgpu_gtt_mgr.c133 lpfn = adev->gart.num_cpu_pages; in amdgpu_gtt_mgr_alloc()
HDamdgpu_job.c87 (*job)->vm_pd_addr = adev->gart.table_addr; in amdgpu_job_alloc_with_ib()
HDmmhub_v1_0.c52 BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); in mmhub_v1_0_init_gart_pt_regs()
53 value = adev->gart.table_addr - adev->gmc.vram_start + in mmhub_v1_0_init_gart_pt_regs()
HDamdgpu_ttm.c1468 flags |= adev->gart.gart_pte_flags; in amdgpu_ttm_tt_pte_flags()
2012 dst_addr = adev->gart.table_addr; in amdgpu_map_buffer()
2344 if (p >= adev->gart.num_cpu_pages) in amdgpu_ttm_gtt_read()
2347 page = adev->gart.pages[p]; in amdgpu_ttm_gtt_read()
2353 kunmap(adev->gart.pages[p]); in amdgpu_ttm_gtt_read()
HDamdgpu_device.c1682 memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM); in amdgpu_device_fill_reset_magic()
1697 return !!memcmp(adev->gart.ptr, adev->reset_magic, in amdgpu_device_check_vram_lost()
HDamdgpu.h1447 struct amdgpu_gart gart; member

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