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/dragonfly/sys/dev/drm/amd/display/dc/calcs/
HDdcn_calcs.c701 int i, input_idx; in dcn_validate_bandwidth() local
830 for (i = 0, input_idx = 0; i < pool->pipe_count; i++) { in dcn_validate_bandwidth()
839 v->underscan_output[input_idx] = false; /* taken care of in recout already*/ in dcn_validate_bandwidth()
840 v->interlace_output[input_idx] = false; in dcn_validate_bandwidth()
842 v->htotal[input_idx] = pipe->stream->timing.h_total; in dcn_validate_bandwidth()
843 v->vtotal[input_idx] = pipe->stream->timing.v_total; in dcn_validate_bandwidth()
844 v->vactive[input_idx] = pipe->stream->timing.v_addressable + in dcn_validate_bandwidth()
846 v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total in dcn_validate_bandwidth()
847 - v->vactive[input_idx] in dcn_validate_bandwidth()
849 v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz / 1000.0f; in dcn_validate_bandwidth()
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