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Searched refs:intr (Results 1 – 25 of 111) sorted by relevance

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/dragonfly/sys/kern/
HDkern_intr.c56 int intr; member
229 register_swi(int intr, inthand2_t *handler, void *arg, const char *name, in register_swi() argument
232 if (intr < FIRST_SOFTINT || intr >= MAX_INTS) in register_swi()
233 panic("register_swi: bad intr %d", intr); in register_swi()
236 cpuid = intr % ncpus; in register_swi()
237 return(register_int(intr, handler, arg, name, serializer, 0, cpuid)); in register_swi()
241 register_swi_mp(int intr, inthand2_t *handler, void *arg, const char *name, in register_swi_mp() argument
244 if (intr < FIRST_SOFTINT || intr >= MAX_INTS) in register_swi_mp()
245 panic("register_swi: bad intr %d", intr); in register_swi_mp()
248 cpuid = intr % ncpus; in register_swi_mp()
[all …]
HDkern_memio.c613 int intr; in random_ioctl() local
626 intr = *(int16_t *)data; in random_ioctl()
629 if (intr < 0 || intr >= MAX_INTS) in random_ioctl()
631 register_randintr(intr); in random_ioctl()
634 intr = *(int16_t *)data; in random_ioctl()
637 if (intr < 0 || intr >= MAX_INTS) in random_ioctl()
639 unregister_randintr(intr); in random_ioctl()
645 intr = *(int16_t *)data; in random_ioctl()
648 if (intr < 0 || intr >= MAX_INTS) in random_ioctl()
650 intr = next_registered_randintr(intr); in random_ioctl()
[all …]
/dragonfly/sys/sys/
HDmachintr.h63 void (*intr_disable)(int intr); /* hardware disable intr */
64 void (*intr_enable)(int intr); /* hardware enable intr */
65 void (*intr_setup)(int intr, int flags);
67 void (*intr_teardown)(int intr); /* tear down intr */
70 (int intr, enum intr_trigger trig, enum intr_polarity pola);
71 int (*legacy_intr_cpuid)(int intr); /* legacy intr target cpu */
73 (int intr, enum intr_trigger trig, enum intr_polarity pola);
82 (int intr, uint64_t *addr, uint32_t *data, int cpuid);
84 (int *intr, int cpuid);
86 (int intr, int cpuid);
[all …]
HDinterrupt.h104 void *register_swi(int intr, inthand2_t *handler, void *arg,
107 void *register_swi_mp(int intr, inthand2_t *handler, void *arg,
110 void *register_int(int intr, inthand2_t *handler, void *arg,
114 long get_interrupt_counter(int intr, int cpuid);
116 void unregister_swi(void *id, int intr, int cpuid);
118 void register_randintr(int intr);
119 void unregister_randintr(int intr);
120 int next_registered_randintr(int intr);
121 void sched_ithd_soft(int intr); /* procedure called from MD */
122 void sched_ithd_hard(int intr); /* procedure called from MD */
[all …]
/dragonfly/sys/platform/pc64/icu/
HDicu_abi.c215 int intr; in icu_abi_stabilize() local
217 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) in icu_abi_stabilize()
218 ICU_INTRDIS(intr); in icu_abi_stabilize()
258 icu_abi_intr_setup(int intr, int flags) in icu_abi_intr_setup() argument
263 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS, in icu_abi_intr_setup()
264 ("icu setup, invalid irq %d", intr)); in icu_abi_intr_setup()
266 map = &icu_irqmaps[mycpuid][intr]; in icu_abi_intr_setup()
269 intr, map->im_type, mycpuid)); in icu_abi_intr_setup()
276 ICU_INTREN(intr); in icu_abi_intr_setup()
282 icu_abi_intr_teardown(int intr) in icu_abi_intr_teardown() argument
[all …]
/dragonfly/sys/platform/pc64/apic/
HDioapic_abi.c630 ioapic_abi_intr_setup(int intr, int flags) in ioapic_abi_intr_setup() argument
637 KASSERT(intr >= 0 && intr < IOAPIC_HWI_VECTORS, in ioapic_abi_intr_setup()
638 ("ioapic setup, invalid irq %d", intr)); in ioapic_abi_intr_setup()
640 map = &ioapic_irqmaps[mycpuid][intr]; in ioapic_abi_intr_setup()
643 intr, map->im_type, mycpuid)); in ioapic_abi_intr_setup()
647 KASSERT(ioapic_irqs[intr].io_addr != NULL, in ioapic_abi_intr_setup()
648 ("ioapic setup, no GSI information, irq %d", intr)); in ioapic_abi_intr_setup()
653 vector = IDT_OFFSET + intr; in ioapic_abi_intr_setup()
664 select = ioapic_irqs[intr].io_idx; in ioapic_abi_intr_setup()
665 value = ioapic_read(ioapic_irqs[intr].io_addr, select); in ioapic_abi_intr_setup()
[all …]
/dragonfly/sys/dev/netif/bnx/
HDif_bnx.c1223 struct bnx_intr_data *intr; in bnx_blockinit() local
1565 intr = &sc->bnx_intr_data[0]; in bnx_blockinit()
1566 bzero(intr->bnx_status_block, BGE_STATUS_BLK_SZ); in bnx_blockinit()
1568 BGE_ADDR_HI(intr->bnx_status_block_paddr)); in bnx_blockinit()
1570 BGE_ADDR_LO(intr->bnx_status_block_paddr)); in bnx_blockinit()
1572 intr = &sc->bnx_intr_data[i]; in bnx_blockinit()
1573 bzero(intr->bnx_status_block, BGE_STATUS_BLK_SZ); in bnx_blockinit()
1575 BGE_ADDR_HI(intr->bnx_status_block_paddr)); in bnx_blockinit()
1577 BGE_ADDR_LO(intr->bnx_status_block_paddr)); in bnx_blockinit()
4137 struct bnx_intr_data *intr = &sc->bnx_intr_data[i]; in bnx_dma_free() local
[all …]
/dragonfly/sys/platform/vkernel64/platform/
HDmachintr.c78 dummy_intr_disable(int intr) in dummy_intr_disable() argument
83 dummy_intr_enable(int intr) in dummy_intr_enable() argument
88 dummy_intr_setup(int intr, int flags) in dummy_intr_setup() argument
93 dummy_intr_teardown(int intr) in dummy_intr_teardown() argument
169 signalintr(int intr) in signalintr() argument
175 atomic_set_int_nonlocked(&gd->gd_fpending, 1 << intr); in signalintr()
181 atomic_clear_int(&gd->gd_fpending, 1 << intr); in signalintr()
182 sched_ithd_hard_virtual(intr); in signalintr()
/dragonfly/sys/dev/drm/include/linux/
HDdma-fence.h75 bool intr, signed long timeout);
132 bool intr, signed long timeout);
134 bool intr, signed long timeout);
137 bool intr, signed long timeout, uint32_t *idx);
140 dma_fence_wait(struct dma_fence *fence, bool intr) in dma_fence_wait() argument
144 ret = dma_fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT); in dma_fence_wait()
/dragonfly/sys/dev/netif/ath/ath/
HDif_ath_alq.h175 struct if_ath_alq_interrupt intr; in if_ath_alq_post_intr() local
180 intr.intr_status = htobe32(status); in if_ath_alq_post_intr()
182 intr.intr_state[i] = htobe32(state[i]); in if_ath_alq_post_intr()
183 intr.intr_syncstate = htobe32(sync_state); in if_ath_alq_post_intr()
185 if_ath_alq_post(alq, ATH_ALQ_INTR_STATUS, sizeof(intr), in if_ath_alq_post_intr()
186 (const char *) &intr); in if_ath_alq_post_intr()
/dragonfly/sys/dev/drm/
HDlinux_wwmutex.c83 bool slow __unused, bool intr) in __wwlock() argument
88 if (intr) in __wwlock()
113 tsleep_interlock(ww, (intr ? PCATCH : 0)); in __wwlock()
153 error = tsleep(ww, PINTERLOCKED | (intr ? PCATCH : 0), in __wwlock()
155 if (intr && (error == EINTR || error == ERESTART)) in __wwlock()
HDlinux_fence.c54 dma_fence_wait_timeout(struct dma_fence *fence, bool intr, long timeout) in dma_fence_wait_timeout() argument
60 return fence->ops->wait(fence, intr, timeout); in dma_fence_wait_timeout()
62 return dma_fence_default_wait(fence, intr, timeout); in dma_fence_wait_timeout()
88 dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) in dma_fence_default_wait() argument
128 if (intr) { in dma_fence_default_wait()
135 err = lksleep(current, fence->lock, intr ? PCATCH : 0, "dmafence", ret); in dma_fence_default_wait()
169 bool intr, long timeout, uint32_t *idx) in dma_fence_wait_any_timeout() argument
206 err = tsleep(current, intr ? PCATCH : 0, "dfwat", ret); in dma_fence_wait_any_timeout()
/dragonfly/sys/dev/netif/igb/
HDif_igb.c3825 struct igb_intr_data *intr; in igb_sysctl_intr_rate() local
3829 intr = &sc->intr_data[i]; in igb_sysctl_intr_rate()
3830 if (intr->intr_use == use) { in igb_sysctl_intr_rate()
3831 rate = intr->intr_rate; in igb_sysctl_intr_rate()
3845 intr = &sc->intr_data[i]; in igb_sysctl_intr_rate()
3846 if (intr->intr_use == use && intr->intr_rate != rate) { in igb_sysctl_intr_rate()
3847 intr->intr_rate = rate; in igb_sysctl_intr_rate()
4139 struct igb_intr_data *intr = &sc->intr_data[i]; in igb_setup_intr() local
4142 error = bus_setup_intr_descr(sc->dev, intr->intr_res, in igb_setup_intr()
4143 INTR_MPSAFE, intr->intr_func, intr->intr_funcarg, in igb_setup_intr()
[all …]
/dragonfly/sys/dev/netif/ix/
HDif_ix.c3890 struct ix_intr_data *intr; in ix_alloc_intr() local
3931 intr = &sc->intr_data[0]; in ix_alloc_intr()
3938 &intr->intr_rid, &intr_flags); in ix_alloc_intr()
3949 if (pci_alloc_msi(sc->dev, &intr->intr_rid, 1, cpu) == 0) { in ix_alloc_intr()
3959 intr->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, in ix_alloc_intr()
3960 &intr->intr_rid, intr_flags); in ix_alloc_intr()
3961 if (intr->intr_res == NULL) { in ix_alloc_intr()
3967 intr->intr_serialize = &sc->main_serialize; in ix_alloc_intr()
3968 intr->intr_cpuid = rman_get_cpuid(intr->intr_res); in ix_alloc_intr()
3970 intr->intr_func = ix_intr_82598; in ix_alloc_intr()
[all …]
/dragonfly/sys/dev/misc/atkbd/
HDatkbd_isa.c55 struct resource *intr; member
120 sc->intr = bus_alloc_legacy_irq_resource(dev, &rid, irq, RF_ACTIVE); in atkbdattach()
121 BUS_SETUP_INTR(device_get_parent(dev), dev, sc->intr, INTR_MPSAFE, in atkbdattach()
141 args[1] = rman_get_start(sc->intr); in atkbdresume()
/dragonfly/sys/dev/drm/radeon/
HDradeon_fence.c488 u64 *target_seq, bool intr, in radeon_fence_wait_seq_timeout() argument
506 if (intr) { in radeon_fence_wait_seq_timeout()
543 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool intr, long timeout) in radeon_fence_wait_timeout() argument
556 return dma_fence_wait(&fence->base, intr); in radeon_fence_wait_timeout()
559 r = radeon_fence_wait_seq_timeout(fence->rdev, seq, intr, timeout); in radeon_fence_wait_timeout()
581 int radeon_fence_wait(struct radeon_fence *fence, bool intr) in radeon_fence_wait() argument
583 long r = radeon_fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT); in radeon_fence_wait()
606 bool intr) in radeon_fence_wait_any() argument
627 r = radeon_fence_wait_seq_timeout(rdev, seq, intr, MAX_SCHEDULE_TIMEOUT); in radeon_fence_wait_any()
1072 static signed long radeon_fence_default_wait(struct dma_fence *f, bool intr, in radeon_fence_default_wait() argument
[all …]
/dragonfly/sys/platform/pc64/include/
HDmsi_var.h8 void msi_setup(int intr, int cpuid);
9 void msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid);
/dragonfly/sys/bus/firewire/
HDfwohci_pci.c254 int intr; in fwohci_pci_attach() local
257 intr = pci_read_config(self, PCIR_INTLINE, 1); in fwohci_pci_attach()
258 if (intr == 0 || intr == 255) in fwohci_pci_attach()
259 device_printf(self, "Invalid irq %d\n", intr); in fwohci_pci_attach()
/dragonfly/contrib/nvi2/ex/
HDex_print.c218 goto intr; in ex_prchars()
238 goto intr; in ex_prchars()
242 goto intr; in ex_prchars()
249 intr: *colp = col; in ex_prchars()
/dragonfly/sys/dev/virtual/vmware/vmxnet3/
HDif_vmx.c670 struct vmxnet3_interrupt *intr) in vmxnet3_alloc_interrupt() argument
679 intr->vmxi_irq = irq; in vmxnet3_alloc_interrupt()
680 intr->vmxi_rid = rid; in vmxnet3_alloc_interrupt()
715 struct vmxnet3_interrupt *intr; in vmxnet3_setup_msix_interrupts() local
719 intr = &sc->vmx_intrs[0]; in vmxnet3_setup_msix_interrupts()
721 for (i = 0; i < sc->vmx_ntxqueues; i++, intr++) { in vmxnet3_setup_msix_interrupts()
723 error = bus_setup_intr(dev, intr->vmxi_irq, INTR_MPSAFE, in vmxnet3_setup_msix_interrupts()
724 vmxnet3_txq_intr, txq, &intr->vmxi_handler, NULL); in vmxnet3_setup_msix_interrupts()
727 bus_describe_intr(dev, intr->vmxi_irq, intr->vmxi_handler, in vmxnet3_setup_msix_interrupts()
729 txq->vxtxq_intr_idx = intr->vmxi_rid - 1; in vmxnet3_setup_msix_interrupts()
[all …]
/dragonfly/sys/dev/drm/ttm/
HDttm_execbuf_util.c94 struct list_head *list, bool intr, in ttm_eu_reserve_buffers() argument
113 ret = __ttm_bo_reserve(bo, intr, (ticket == NULL), ticket); in ttm_eu_reserve_buffers()
142 if (ret == -EDEADLK && intr) { in ttm_eu_reserve_buffers()
/dragonfly/sys/dev/sound/pci/
HDenvy24.c171 u_int16_t intr[2]; member
1204 u_int32_t mask, intr; in envy24_updintr() local
1237 intr = envy24_rdmt(sc, ENVY24_MT_INT, 1); in envy24_updintr()
1239 device_printf(sc->dev, "envy24_updintr():intr = 0x%02x, mask = 0x%02x\n", intr, mask); in envy24_updintr()
1241 envy24_wrmt(sc, ENVY24_MT_INT, intr & mask, 1); in envy24_updintr()
1254 u_int32_t mask, intr;
1263 intr = envy24_rdmt(sc, ENVY24_MT_INT, 1);
1264 envy24_wrmt(sc, ENVY24_MT_INT, intr | mask, 1);
1273 u_int32_t mask, stat, intr, rtn; in envy24_checkintr() local
1278 intr = envy24_rdmt(sc, ENVY24_MT_INT, 1); in envy24_checkintr()
[all …]
HDenvy24ht.c170 u_int16_t intr[2]; member
1158 u_int32_t mask, intr; in envy24ht_updintr() local
1191 intr = envy24ht_rdmt(sc, ENVY24HT_MT_INT_MASK, 1); in envy24ht_updintr()
1193 device_printf(sc->dev, "envy24ht_updintr():intr = 0x%02x, mask = 0x%02x\n", intr, mask); in envy24ht_updintr()
1195 envy24ht_wrmt(sc, ENVY24HT_MT_INT_MASK, intr & mask, 1); in envy24ht_updintr()
1208 u_int32_t mask, intr; in envy24ht_maskintr() local
1217 intr = envy24ht_rdmt(sc, ENVY24HT_MT_INT, 1); in envy24ht_maskintr()
1218 envy24ht_wrmt(sc, ENVY24HT_MT_INT, intr | mask, 1); in envy24ht_maskintr()
1227 u_int32_t mask, stat, intr, rtn; in envy24ht_checkintr() local
1232 intr = envy24ht_rdmt(sc, ENVY24HT_MT_INT_STAT, 1); in envy24ht_checkintr()
[all …]
/dragonfly/games/arithmetic/
HDarithmetic.c75 static void intr(int) __dead2;
137 signal(SIGINT, intr); in main()
151 intr(__unused int sig) in intr() function
/dragonfly/sys/platform/pc64/x86_64/
HDmsi.c431 msi_setup(int intr, int cpuid) in msi_setup() argument
433 setidt(IDT_OFFSET + intr, msi_intr[intr], in msi_setup()
438 msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid) in msi_map() argument
442 vector = IDT_OFFSET + intr; in msi_map()

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