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Searched refs:levels (Results 1 – 25 of 99) sorted by relevance

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/dragonfly/sys/dev/drm/radeon/
HDrv730_dpm.c247 &table->ACPIState.levels[0].vddc); in rv730_populate_smc_acpi_state()
248 table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ? in rv730_populate_smc_acpi_state()
250 table->ACPIState.levels[0].gen2XSP = in rv730_populate_smc_acpi_state()
254 &table->ACPIState.levels[0].vddc); in rv730_populate_smc_acpi_state()
255 table->ACPIState.levels[0].gen2PCIE = 0; in rv730_populate_smc_acpi_state()
297 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in rv730_populate_smc_acpi_state()
298 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2); in rv730_populate_smc_acpi_state()
299 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3); in rv730_populate_smc_acpi_state()
300 table->ACPIState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv730_populate_smc_acpi_state()
301 table->ACPIState.levels[0].mclk.mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv730_populate_smc_acpi_state()
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HDrv740_dpm.c335 &table->ACPIState.levels[0].vddc); in rv740_populate_smc_acpi_state()
336 table->ACPIState.levels[0].gen2PCIE = in rv740_populate_smc_acpi_state()
339 table->ACPIState.levels[0].gen2XSP = in rv740_populate_smc_acpi_state()
343 &table->ACPIState.levels[0].vddc); in rv740_populate_smc_acpi_state()
344 table->ACPIState.levels[0].gen2PCIE = 0; in rv740_populate_smc_acpi_state()
374 … table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv740_populate_smc_acpi_state()
375 … table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv740_populate_smc_acpi_state()
376 … table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv740_populate_smc_acpi_state()
377 … table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv740_populate_smc_acpi_state()
378 table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv740_populate_smc_acpi_state()
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HDcypress_dpm.c775 &smc_state->levels[0], in cypress_convert_power_state_to_smc()
782 &smc_state->levels[1], in cypress_convert_power_state_to_smc()
789 &smc_state->levels[2], in cypress_convert_power_state_to_smc()
794 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1; in cypress_convert_power_state_to_smc()
795 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2; in cypress_convert_power_state_to_smc()
796 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3; in cypress_convert_power_state_to_smc()
799 smc_state->levels[0].ACIndex = 2; in cypress_convert_power_state_to_smc()
800 smc_state->levels[1].ACIndex = 3; in cypress_convert_power_state_to_smc()
801 smc_state->levels[2].ACIndex = 4; in cypress_convert_power_state_to_smc()
803 smc_state->levels[0].ACIndex = 0; in cypress_convert_power_state_to_smc()
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HDsumo_dpm.c350 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
414 m_a = asi * ps->levels[i].sclk / 100; in sumo_program_at()
673 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1]; in sumo_patch_boost_state()
765 sumo_program_power_level(rdev, &new_ps->levels[i], i); in sumo_program_power_levels_0_to_n()
847 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in sumo_set_uvd_clock_before_set_eng_clock()
848 current_ps->levels[current_ps->num_levels - 1].sclk) in sumo_set_uvd_clock_before_set_eng_clock()
865 if (new_ps->levels[new_ps->num_levels - 1].sclk < in sumo_set_uvd_clock_after_set_eng_clock()
866 current_ps->levels[current_ps->num_levels - 1].sclk) in sumo_set_uvd_clock_after_set_eng_clock()
1056 current_vddc = current_ps->levels[current_index].vddc_index; in sumo_patch_thermal_state()
1057 current_sclk = current_ps->levels[current_index].sclk; in sumo_patch_thermal_state()
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HDrv770_dpm.c294 smc_state->levels[i].aT = cpu_to_be32(a_t); in rv770_populate_smc_t()
300 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].aT = in rv770_populate_smc_t()
314 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); in rv770_populate_smc_sp()
316 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].bSP = in rv770_populate_smc_sp()
690 &smc_state->levels[0], in rv770_convert_power_state_to_smc()
697 &smc_state->levels[1], in rv770_convert_power_state_to_smc()
704 &smc_state->levels[2], in rv770_convert_power_state_to_smc()
709 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1; in rv770_convert_power_state_to_smc()
710 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2; in rv770_convert_power_state_to_smc()
711 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3; in rv770_convert_power_state_to_smc()
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HDtrinity_dpm.c854 trinity_program_power_level(rdev, &new_ps->levels[i], i); in trinity_program_power_levels_0_to_n()
974 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
975 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
988 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
989 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
1336 ps->levels[0] = pi->boot_pl; in trinity_patch_boot_state()
1359 pi->current_ps.levels[0] = pi->boot_pl; in trinity_construct_boot_state()
1414 current_vddc = current_ps->levels[current_index].vddc_index; in trinity_patch_thermal_state()
1415 current_sclk = current_ps->levels[current_index].sclk; in trinity_patch_thermal_state()
1421 ps->levels[0].vddc_index = current_vddc; in trinity_patch_thermal_state()
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HDni_dpm.c1690 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = in ni_populate_smc_initial_state()
1692 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 = in ni_populate_smc_initial_state()
1694 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = in ni_populate_smc_initial_state()
1696 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 = in ni_populate_smc_initial_state()
1698 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = in ni_populate_smc_initial_state()
1700 table->initialState.levels[0].mclk.vDLL_CNTL = in ni_populate_smc_initial_state()
1702 table->initialState.levels[0].mclk.vMPLL_SS = in ni_populate_smc_initial_state()
1704 table->initialState.levels[0].mclk.vMPLL_SS2 = in ni_populate_smc_initial_state()
1706 table->initialState.levels[0].mclk.mclk_value = in ni_populate_smc_initial_state()
1709 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = in ni_populate_smc_initial_state()
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HDsi_dpm.c2316 smc_state->levels[0].dpm2.MaxPS = 0; in si_populate_power_containment_values()
2317 smc_state->levels[0].dpm2.NearTDPDec = 0; in si_populate_power_containment_values()
2318 smc_state->levels[0].dpm2.AboveSafeInc = 0; in si_populate_power_containment_values()
2319 smc_state->levels[0].dpm2.BelowSafeInc = 0; in si_populate_power_containment_values()
2320 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; in si_populate_power_containment_values()
2370 …smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / ma… in si_populate_power_containment_values()
2371 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; in si_populate_power_containment_values()
2372 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; in si_populate_power_containment_values()
2373 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; in si_populate_power_containment_values()
2374 … smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); in si_populate_power_containment_values()
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HDkv_dpm.c1713 if ((table->entries[i].clk >= new_ps->levels[0].sclk) || in kv_set_valid_clock_range()
1721 … if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1727 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1728 … (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1738 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || in kv_set_valid_clock_range()
1747 new_ps->levels[new_ps->num_levels - 1].sclk) in kv_set_valid_clock_range()
1753 if ((new_ps->levels[0].sclk - in kv_set_valid_clock_range()
1756 new_ps->levels[new_ps->num_levels -1].sclk)) in kv_set_valid_clock_range()
2185 if (ps->levels[i].sclk < sclk) in kv_apply_state_adjust_rules()
2186 ps->levels[i].sclk = sclk; in kv_apply_state_adjust_rules()
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/dragonfly/crypto/libressl/crypto/x509/
HDpcy_tree.c107 curr = tree->levels + tree->nlevel; in tree_print()
111 BIO_printf(err, "Printing Up to Level %ld\n", curr - tree->levels); in tree_print()
112 for (plev = tree->levels; plev != curr; plev++) { in tree_print()
114 plev - tree->levels, plev->flags); in tree_print()
220 tree->levels = calloc(n, sizeof(X509_POLICY_LEVEL)); in tree_init()
226 if (!tree->levels) { in tree_init()
233 level = tree->levels; in tree_init()
464 if (curr == tree->levels) { in tree_prune()
509 curr = tree->levels + tree->nlevel - 1; in tree_calculate_authority_set()
520 curr = tree->levels; in tree_calculate_authority_set()
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/dragonfly/lib/libc/db/btree/
HDbt_debug.c250 int levels; in __bt_stat() local
275 for (i = P_ROOT, levels = 0 ;; ++levels) { in __bt_stat()
278 if (levels == 0) in __bt_stat()
279 levels = 1; in __bt_stat()
288 levels, levels == 1 ? "" : "s", nkeys); in __bt_stat()
/dragonfly/sys/dev/drm/amd/amdgpu/
HDsi_dpm.c2413 smc_state->levels[0].dpm2.MaxPS = 0; in si_populate_power_containment_values()
2414 smc_state->levels[0].dpm2.NearTDPDec = 0; in si_populate_power_containment_values()
2415 smc_state->levels[0].dpm2.AboveSafeInc = 0; in si_populate_power_containment_values()
2416 smc_state->levels[0].dpm2.BelowSafeInc = 0; in si_populate_power_containment_values()
2417 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; in si_populate_power_containment_values()
2466 …smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / ma… in si_populate_power_containment_values()
2467 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; in si_populate_power_containment_values()
2468 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; in si_populate_power_containment_values()
2469 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; in si_populate_power_containment_values()
2470 … smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); in si_populate_power_containment_values()
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/dragonfly/sys/dev/acpica/
HDacpi_thermal.c1097 struct cf_level *levels; in acpi_tz_cpufreq_update() local
1100 levels = kmalloc(CPUFREQ_MAX_LEVELS * sizeof(*levels), M_TEMP, M_NOWAIT); in acpi_tz_cpufreq_update()
1101 if (levels == NULL) in acpi_tz_cpufreq_update()
1114 error = CPUFREQ_GET(dev, &levels[0]); in acpi_tz_cpufreq_update()
1117 freq = levels[0].total_set.freq; in acpi_tz_cpufreq_update()
1121 error = CPUFREQ_LEVELS(dev, levels, &num_levels); in acpi_tz_cpufreq_update()
1129 perf = 100 * freq / levels[0].total_set.freq - req; in acpi_tz_cpufreq_update()
1134 desired_freq = levels[0].total_set.freq * perf / 100; in acpi_tz_cpufreq_update()
1139 if (levels[i].total_set.freq <= desired_freq) in acpi_tz_cpufreq_update()
1158 if (levels[i].total_set.freq >= desired_freq) in acpi_tz_cpufreq_update()
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/dragonfly/test/stress/stress2/tools/
HDfstool.c138 int c, levels = 1, leave = 0; in main() local
153 levels = atoi(optarg); in main()
179 max = levels; in main()
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
HDfiji_smumgr.c1028 struct SMU73_Discrete_GraphicsLevel *levels = in fiji_populate_all_graphic_levels() local
1039 &levels[i]); in fiji_populate_all_graphic_levels()
1045 levels[i].DeepSleepDivId = 0; in fiji_populate_all_graphic_levels()
1049 levels[0].EnabledForActivity = 1; in fiji_populate_all_graphic_levels()
1052 levels[dpm_table->sclk_table.count - 1].DisplayWatermark = in fiji_populate_all_graphic_levels()
1066 levels[i].pcieDpmLevel = in fiji_populate_all_graphic_levels()
1091 levels[i].pcieDpmLevel = hightest_pcie_level_enabled; in fiji_populate_all_graphic_levels()
1094 levels[0].pcieDpmLevel = lowest_pcie_level_enabled; in fiji_populate_all_graphic_levels()
1097 levels[1].pcieDpmLevel = mid_pcie_level_enabled; in fiji_populate_all_graphic_levels()
1100 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels, in fiji_populate_all_graphic_levels()
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HDpolaris10_smumgr.c990 struct SMU74_Discrete_GraphicsLevel *levels = in polaris10_populate_all_graphic_levels() local
1010 levels[i].DeepSleepDivId = 0; in polaris10_populate_all_graphic_levels()
1029 levels[i].pcieDpmLevel = in polaris10_populate_all_graphic_levels()
1054 levels[i].pcieDpmLevel = hightest_pcie_level_enabled; in polaris10_populate_all_graphic_levels()
1057 levels[0].pcieDpmLevel = lowest_pcie_level_enabled; in polaris10_populate_all_graphic_levels()
1060 levels[1].pcieDpmLevel = mid_pcie_level_enabled; in polaris10_populate_all_graphic_levels()
1063 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels, in polaris10_populate_all_graphic_levels()
1133 struct SMU74_Discrete_MemoryLevel *levels = in polaris10_populate_all_memory_levels() local
1143 &levels[i]); in polaris10_populate_all_memory_levels()
1145 levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; in polaris10_populate_all_memory_levels()
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HDvegam_smumgr.c878 struct SMU75_Discrete_GraphicsLevel *levels = in vegam_populate_all_graphic_levels() local
896 levels[i].UpHyst = (uint8_t) in vegam_populate_all_graphic_levels()
898 levels[i].DownHyst = (uint8_t) in vegam_populate_all_graphic_levels()
902 levels[i].DeepSleepDivId = 0; in vegam_populate_all_graphic_levels()
914 levels[i].EnabledForActivity = in vegam_populate_all_graphic_levels()
923 levels[i].pcieDpmLevel = in vegam_populate_all_graphic_levels()
948 levels[i].pcieDpmLevel = hightest_pcie_level_enabled; in vegam_populate_all_graphic_levels()
951 levels[0].pcieDpmLevel = lowest_pcie_level_enabled; in vegam_populate_all_graphic_levels()
954 levels[1].pcieDpmLevel = mid_pcie_level_enabled; in vegam_populate_all_graphic_levels()
957 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels, in vegam_populate_all_graphic_levels()
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/dragonfly/contrib/gcc-4.7/libgomp/
HDfortran.c380 omp_set_max_active_levels_ (const int32_t *levels) in omp_set_max_active_levels_() argument
382 omp_set_max_active_levels (*levels); in omp_set_max_active_levels_()
386 omp_set_max_active_levels_8_ (const int64_t *levels) in omp_set_max_active_levels_8_() argument
388 omp_set_max_active_levels (TO_INT (*levels)); in omp_set_max_active_levels_8_()
/dragonfly/contrib/gcc-8.0/libgomp/
HDfortran.c392 omp_set_max_active_levels_ (const int32_t *levels) in omp_set_max_active_levels_() argument
394 omp_set_max_active_levels (*levels); in omp_set_max_active_levels_()
398 omp_set_max_active_levels_8_ (const int64_t *levels) in omp_set_max_active_levels_8_() argument
400 omp_set_max_active_levels (TO_INT (*levels)); in omp_set_max_active_levels_8_()
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
HDsmu8_hwmgr.c1310 return smu8_ps->levels[0].engineClock; in smu8_dpm_get_sclk()
1312 return smu8_ps->levels[smu8_ps->level-1].engineClock; in smu8_dpm_get_sclk()
1324 smu8_ps->levels[0] = data->boot_power_level; in smu8_dpm_patch_boot_state()
1346 smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk; in smu8_dpm_get_pp_table_entry_callback()
1347 smu8_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v; in smu8_dpm_get_pp_table_entry_callback()
1352 smu8_ps->levels[index].dsDividerIndex = 5; in smu8_dpm_get_pp_table_entry_callback()
1353 smu8_ps->levels[index].ssDividerIndex = 5; in smu8_dpm_get_pp_table_entry_callback()
1563 level->coreClock = ps->levels[level_index].engineClock; in smu8_get_performance_level()
1567 if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) { in smu8_get_performance_level()
1568 level->coreClock = ps->levels[i].engineClock; in smu8_get_performance_level()
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HDsmu10_hwmgr.c723 smu10_ps->levels[index].engine_clock = 0; in smu10_dpm_get_pp_table_entry_callback()
725 smu10_ps->levels[index].vddc_index = 0; in smu10_dpm_get_pp_table_entry_callback()
729 smu10_ps->levels[index].ds_divider_index = 5; in smu10_dpm_get_pp_table_entry_callback()
730 smu10_ps->levels[index].ss_divider_index = 5; in smu10_dpm_get_pp_table_entry_callback()
929 … clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index)); in smu10_get_current_shallow_sleep_clocks()
930 …clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1… in smu10_get_current_shallow_sleep_clocks()
/dragonfly/contrib/libpcap/
HDoptimize.c271 struct block **levels; member
395 b->link = opt_state->levels[level]; in find_levels_r()
396 opt_state->levels[level] = b; in find_levels_r()
408 memset((char *)opt_state->levels, 0, opt_state->n_blocks * sizeof(*opt_state->levels)); in find_levels()
445 for (b = opt_state->levels[level]; b; b = b->link) { in find_dom()
490 for (b = opt_state->levels[level]; b != 0; b = b->link) { in find_edom()
518 for (b = opt_state->levels[level]; b; b = b->link) { in find_closure()
695 for (p = opt_state->levels[i]; p; p = p->link) { in find_ud()
701 for (p = opt_state->levels[i]; p; p = p->link) { in find_ud()
2087 for (p = opt_state->levels[i]; p; p = p->link) in opt_blks()
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/dragonfly/sys/vfs/ext2fs/
HDext2_htree.c122 int levels = 0; in ext2_htree_check_next() local
133 levels++; in ext2_htree_check_next()
142 while (levels > 0) { in ext2_htree_check_next()
143 levels--; in ext2_htree_check_next()
270 uint32_t levels, cnt; in ext2_htree_find_leaf() local
302 if ((levels = rootp->h_info.h_ind_levels) > 1) in ext2_htree_find_leaf()
332 if (levels == 0) in ext2_htree_find_leaf()
334 levels--; in ext2_htree_find_leaf()
/dragonfly/sys/dev/acpica/acpi_video/
HDacpi_video.c972 int num, i, n, *levels; in vo_get_brightness_levels() local
992 levels = AcpiOsAllocate(num * sizeof(*levels)); in vo_get_brightness_levels()
993 if (levels == NULL) in vo_get_brightness_levels()
996 if (acpi_PkgInt32(res, i, &levels[n]) == 0) in vo_get_brightness_levels()
999 AcpiOsFree(levels); in vo_get_brightness_levels()
1002 *levelp = levels; in vo_get_brightness_levels()
/dragonfly/contrib/zstd/
HDCHANGELOG5 perf: stronger --long mode at high compression levels, by @senhuang42
6 perf: stronger --patch-from at high compression levels, thanks to --long improvements
7 perf: faster dictionary compression at medium compression levels, by @felixhandte
63 fix : Compression ratio regression on huge files (> 3 GB) using high levels (--ultra) and multithre…
217 fix : performance of dictionary compression for small input < 4 KB at levels 9 and 10
239 perf: slightly improved high compression levels (notably level 19)
254 perf: better compression at levels 13-15
260 api : compression levels can be negative, for even more speed
270 perf: faster zstd_opt strategy (levels 16-19)
288 fix : 32-bits build can now decode large offsets (levels 21+)
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