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Searched refs:mmCRTC_UPDATE_LOCK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDdce_v10_0.c480 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v10_0_disable_dce()
484 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v10_0_disable_dce()
HDdce_v11_0.c506 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v11_0_disable_dce()
510 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v11_0_disable_dce()
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_d.h1015 #define mmCRTC_UPDATE_LOCK 0x1BB5 macro
HDdce_8_0_d.h508 #define mmCRTC_UPDATE_LOCK 0x1bb5 macro
HDdce_10_0_d.h588 #define mmCRTC_UPDATE_LOCK 0x1bb5 macro
HDdce_11_0_d.h490 #define mmCRTC_UPDATE_LOCK 0x1bb5 macro
HDdce_11_2_d.h497 #define mmCRTC_UPDATE_LOCK 0x1bb5 macro