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Searched refs:mmDCP5_REGAMMA_CONTROL (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_d.h2447 #define mmDCP5_REGAMMA_CONTROL 0x49A0 macro
HDdce_8_0_d.h2605 #define mmDCP5_REGAMMA_CONTROL 0x49a0 macro
HDdce_10_0_d.h3384 #define mmDCP5_REGAMMA_CONTROL 0x44a0 macro
HDdce_11_0_d.h3145 #define mmDCP5_REGAMMA_CONTROL 0x44a0 macro
HDdce_11_2_d.h4376 #define mmDCP5_REGAMMA_CONTROL 0x44a0 macro
HDdce_12_0_offset.h7656 #define mmDCP5_REGAMMA_CONTROL … macro