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Searched refs:mmDEGAMMA_CONTROL (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDdce_v10_0.c2126 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2130 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
HDdce_v11_0.c2162 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2166 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_d.h2475 #define mmDEGAMMA_CONTROL 0x1A58 macro
HDdce_8_0_d.h2151 #define mmDEGAMMA_CONTROL 0x1a58 macro
HDdce_10_0_d.h3000 #define mmDEGAMMA_CONTROL 0x1a58 macro
HDdce_11_0_d.h2754 #define mmDEGAMMA_CONTROL 0x1a58 macro
HDdce_11_2_d.h3985 #define mmDEGAMMA_CONTROL 0x1a58 macro