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Searched refs:mmDP0_DP_VID_TIMING (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_d.h3166 #define mmDP0_DP_VID_TIMING 0x1CC9 macro
HDdce_8_0_d.h3812 #define mmDP0_DP_VID_TIMING 0x1cc9 macro
HDdce_10_0_d.h4444 #define mmDP0_DP_VID_TIMING 0x4aa8 macro
HDdce_11_0_d.h4408 #define mmDP0_DP_VID_TIMING 0x4aa8 macro
HDdce_11_2_d.h5640 #define mmDP0_DP_VID_TIMING 0x4aa8 macro
HDdce_12_0_offset.h10212 #define mmDP0_DP_VID_TIMING … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
HDdcn_1_0_offset.h8355 #define mmDP0_DP_VID_TIMING … macro