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Searched refs:mmDP1_DP_DPHY_SCRAM_CNTL (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_8_0_d.h3925 #define mmDP1_DP_DPHY_SCRAM_CNTL 0x1fd5 macro
HDdce_10_0_d.h4557 #define mmDP1_DP_DPHY_SCRAM_CNTL 0x4bb6 macro
HDdce_11_0_d.h4549 #define mmDP1_DP_DPHY_SCRAM_CNTL 0x4bb6 macro
HDdce_11_2_d.h5781 #define mmDP1_DP_DPHY_SCRAM_CNTL 0x4bb6 macro
HDdce_12_0_offset.h10524 #define mmDP1_DP_DPHY_SCRAM_CNTL … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
HDdcn_1_0_offset.h8693 #define mmDP1_DP_DPHY_SCRAM_CNTL … macro