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Searched refs:mmDP_DTO1_PHASE (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_d.h3541 #define mmDP_DTO1_PHASE 0x0145 macro
HDdce_8_0_d.h1042 #define mmDP_DTO1_PHASE 0x145 macro
HDdce_10_0_d.h1200 #define mmDP_DTO1_PHASE 0x145 macro
HDdce_11_0_d.h1012 #define mmDP_DTO1_PHASE 0x145 macro
HDdce_11_2_d.h1087 #define mmDP_DTO1_PHASE 0x145 macro
HDdce_12_0_offset.h782 #define mmDP_DTO1_PHASE … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
HDdcn_1_0_offset.h582 #define mmDP_DTO1_PHASE … macro