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Searched refs:mmFBC_MISC (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce110/
HDdce110_compressor.c251 misc_value = dm_read_reg(compressor->ctx, mmFBC_MISC); in dce110_compressor_enable_fbc()
260 dm_write_reg(compressor->ctx, mmFBC_MISC, misc_value); in dce110_compressor_enable_fbc()
308 value = dm_read_reg(compressor->ctx, mmFBC_MISC); in dce110_compressor_is_fbc_enabled_in_hw()
/dragonfly/sys/dev/drm/amd/amdgpu/
HDmxgpu_vi.c102 mmFBC_MISC, 0x1f311fff, 0x12300000,
234 mmFBC_MISC, 0x1f311fff, 0x12300000,
HDdce_v11_0.c123 mmFBC_MISC, 0x1f311fff, 0x14300000,
135 mmFBC_MISC, 0x1f311fff, 0x14302000,
143 mmFBC_MISC, 0x9f313fff, 0x14302008,
151 mmFBC_MISC, 0x9f313fff, 0x14302008,
HDdce_v10_0.c122 mmFBC_MISC, 0x1f311fff, 0x12300000,
136 mmFBC_MISC, 0x1f311fff, 0x12300000,
/dragonfly/sys/dev/drm/amd/display/dc/dce112/
HDdce112_compressor.c453 value = dm_read_reg(compressor->ctx, mmFBC_MISC); in dce112_compressor_is_fbc_enabled_in_hw()
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_d.h3646 #define mmFBC_MISC 0x16F0 macro
HDdce_8_0_d.h4361 #define mmFBC_MISC 0x16f0 macro
HDdce_10_0_d.h5042 #define mmFBC_MISC 0x2a2 macro
HDdce_11_0_d.h5121 #define mmFBC_MISC 0x2a2 macro
HDdce_11_2_d.h6361 #define mmFBC_MISC 0x2a2 macro
HDdce_12_0_offset.h902 #define mmFBC_MISC … macro