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Searched refs:mmFMT_BIT_DEPTH_CONTROL (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_d.h3777 #define mmFMT_BIT_DEPTH_CONTROL 0x1BF2 macro
HDdce_8_0_d.h4421 #define mmFMT_BIT_DEPTH_CONTROL 0x1bf2 macro
HDdce_10_0_d.h5102 #define mmFMT_BIT_DEPTH_CONTROL 0x1bf2 macro
HDdce_11_0_d.h5160 #define mmFMT_BIT_DEPTH_CONTROL 0x1bf2 macro
HDdce_11_2_d.h6402 #define mmFMT_BIT_DEPTH_CONTROL 0x1bf2 macro
/dragonfly/sys/dev/drm/amd/amdgpu/
HDdce_v10_0.c563 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_fmt()
HDdce_v11_0.c589 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_fmt()