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Searched refs:mmGRPH_CONTROL (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce100/
HDdce100_resource.c108 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
112 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
116 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
120 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
124 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
128 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
/dragonfly/sys/dev/drm/amd/display/dc/dce80/
HDdce80_resource.c114 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
120 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
126 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
132 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
138 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
144 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
/dragonfly/sys/dev/drm/amd/display/dc/dce112/
HDdce112_resource.c120 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
124 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
128 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
132 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
136 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
140 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
/dragonfly/sys/dev/drm/amd/display/dc/dce110/
HDdce110_resource.c118 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
122 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
126 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
130 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
134 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
138 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_d.h3826 #define mmGRPH_CONTROL 0x1A01 macro
HDdce_8_0_d.h1542 #define mmGRPH_CONTROL 0x1a01 macro
HDdce_10_0_d.h2391 #define mmGRPH_CONTROL 0x1a01 macro
HDdce_11_0_d.h2285 #define mmGRPH_CONTROL 0x1a01 macro
HDdce_11_2_d.h3516 #define mmGRPH_CONTROL 0x1a01 macro
/dragonfly/sys/dev/drm/amd/amdgpu/
HDdce_v10_0.c1997 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v10_0_crtc_do_set_base()
HDdce_v11_0.c2039 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v11_0_crtc_do_set_base()