Home
last modified time | relevance | path

Searched refs:mmGRPH_INTERRUPT_CONTROL (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDdce_v10_0.c3081 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); in dce_v10_0_set_pageflip_irq_state()
3083 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v10_0_set_pageflip_irq_state()
3086 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v10_0_set_pageflip_irq_state()
HDdce_v11_0.c3207 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); in dce_v11_0_set_pageflip_irq_state()
3209 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v11_0_set_pageflip_irq_state()
3212 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v11_0_set_pageflip_irq_state()
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_d.h3831 #define mmGRPH_INTERRUPT_CONTROL 0x1A17 macro
HDdce_8_0_d.h1689 #define mmGRPH_INTERRUPT_CONTROL 0x1a17 macro
HDdce_10_0_d.h2538 #define mmGRPH_INTERRUPT_CONTROL 0x1a17 macro
HDdce_11_0_d.h2432 #define mmGRPH_INTERRUPT_CONTROL 0x1a17 macro
HDdce_11_2_d.h3663 #define mmGRPH_INTERRUPT_CONTROL 0x1a17 macro