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Searched refs:mmSCL5_SCL_CONTROL (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
HDdce_6_0_d.h4263 #define mmSCL5_SCL_CONTROL 0x4A44 macro
HDdce_8_0_d.h4852 #define mmSCL5_SCL_CONTROL 0x4a44 macro
HDdce_10_0_d.h5568 #define mmSCL5_SCL_CONTROL 0x4544 macro
HDdce_11_0_d.h5626 #define mmSCL5_SCL_CONTROL 0x4544 macro
HDdce_11_2_d.h6953 #define mmSCL5_SCL_CONTROL 0x4544 macro
HDdce_12_0_offset.h7874 #define mmSCL5_SCL_CONTROL … macro