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Searched refs:pipe_bpp (Results 1 – 14 of 14) sorted by relevance

/dragonfly/sys/dev/drm/i915/
HDintel_dsi_pll.c255 static void assert_bpp_mismatch(enum mipi_dsi_pixel_format fmt, int pipe_bpp) in assert_bpp_mismatch() argument
259 WARN(bpp != pipe_bpp, in assert_bpp_mismatch()
261 bpp, pipe_bpp); in assert_bpp_mismatch()
264 static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp, in vlv_dsi_get_pclk() argument
323 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); in vlv_dsi_get_pclk()
325 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); in vlv_dsi_get_pclk()
330 static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp, in bxt_dsi_get_pclk() argument
340 if (!pipe_bpp) { in bxt_dsi_get_pclk()
352 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); in bxt_dsi_get_pclk()
354 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); in bxt_dsi_get_pclk()
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HDintel_dp_mst.c65 pipe_config->pipe_bpp = bpp; in intel_dp_mst_compute_config()
288 pipe_config->pipe_bpp = 18; in intel_dp_mst_enc_get_config()
291 pipe_config->pipe_bpp = 24; in intel_dp_mst_enc_get_config()
294 pipe_config->pipe_bpp = 30; in intel_dp_mst_enc_get_config()
297 pipe_config->pipe_bpp = 36; in intel_dp_mst_enc_get_config()
HDintel_hdmi.c614 static bool gcp_default_phase_possible(int pipe_bpp, in gcp_default_phase_possible() argument
619 switch (pipe_bpp) { in gcp_default_phase_possible()
670 if (gcp_default_phase_possible(crtc_state->pipe_bpp, in intel_hdmi_set_gcp_infoframe()
897 if (crtc_state->pipe_bpp > 24) in intel_hdmi_prepare()
1066 if (pipe_config->pipe_bpp > 24 && in ibx_enable_hdmi()
1112 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
1124 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
1465 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && !force_dvi && in intel_hdmi_compute_config()
1482 pipe_config->pipe_bpp = desired_bpp; in intel_hdmi_compute_config()
HDintel_ddi.c1287 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) in ddi_dotclock_get()
1516 switch (crtc_state->pipe_bpp) { in intel_ddi_set_pipe_settings()
1566 switch (crtc_state->pipe_bpp) { in intel_ddi_enable_transcoder_func()
2569 pipe_config->pipe_bpp = 18; in intel_ddi_get_config()
2572 pipe_config->pipe_bpp = 24; in intel_ddi_get_config()
2575 pipe_config->pipe_bpp = 30; in intel_ddi_get_config()
2578 pipe_config->pipe_bpp = 36; in intel_ddi_get_config()
2617 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { in intel_ddi_get_config()
2632 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); in intel_ddi_get_config()
2633 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; in intel_ddi_get_config()
HDintel_lvds.c292 if (pipe_config->dither && pipe_config->pipe_bpp == 18) in intel_pre_enable_lvds()
408 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { in intel_lvds_compute_config()
410 pipe_config->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
411 pipe_config->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
HDintel_dsi.h143 u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
HDintel_crt.c369 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { in hsw_crt_compute_config()
374 pipe_config->pipe_bpp = 24; in hsw_crt_compute_config()
HDintel_display.c6158 pipe_config->pipe_bpp); in ironlake_fdi_compute_config()
6162 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, in ironlake_fdi_compute_config()
6166 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { in ironlake_fdi_compute_config()
6167 pipe_config->pipe_bpp -= 2*3; in ironlake_fdi_compute_config()
6169 pipe_config->pipe_bpp); in ironlake_fdi_compute_config()
6188 if (pipe_config->pipe_bpp > 24) in pipe_config_supports_ips()
7105 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) in i9xx_set_pipeconf()
7109 switch (intel_crtc->config->pipe_bpp) { in i9xx_set_pipeconf()
7512 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
7515 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
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HDintel_dsi.c1109 pipe_config->pipe_bpp = in bxt_dsi_get_pipe_config()
1112 bpp = pipe_config->pipe_bpp; in bxt_dsi_get_pipe_config()
1249 pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp, in intel_dsi_get_config()
HDintel_dp.c1593 bpp = pipe_config->pipe_bpp; in intel_dp_compute_bpp()
1601 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc; in intel_dp_compute_bpp()
1602 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3; in intel_dp_compute_bpp()
1604 pipe_config->pipe_bpp); in intel_dp_compute_bpp()
1787 pipe_config->pipe_bpp = bpp; in intel_dp_compute_config()
2659 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { in intel_dp_get_config()
2674 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); in intel_dp_get_config()
2675 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; in intel_dp_get_config()
HDintel_tv.c886 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
HDintel_drv.h713 int pipe_bpp; member
HDintel_panel.c370 if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18) in intel_gmch_panel_fitting()
HDintel_sdvo.c1130 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()