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Searched refs:rlc (Results 1 – 15 of 15) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
HDgfx_v9_0.c462 kfree(adev->gfx.rlc.register_list_format); in gfx_v9_0_free_microcode()
472 …adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size… in gfx_v9_0_init_rlc_ext_microcode()
473 …adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl… in gfx_v9_0_init_rlc_ext_microcode()
476 …adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_b… in gfx_v9_0_init_rlc_ext_microcode()
477 …adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_o… in gfx_v9_0_init_rlc_ext_microcode()
480 …adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_b… in gfx_v9_0_init_rlc_ext_microcode()
481 …adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_o… in gfx_v9_0_init_rlc_ext_microcode()
482 adev->gfx.rlc.reg_list_format_direct_reg_list_length = in gfx_v9_0_init_rlc_ext_microcode()
562 adev->gfx.rlc.is_rlc_v2_1 = true; in gfx_v9_0_init_microcode()
566 adev->gfx.rlc.save_and_restore_offset = in gfx_v9_0_init_microcode()
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HDamdgpu_ucode.c370 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; in amdgpu_ucode_init_single_fw()
371 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl, in amdgpu_ucode_init_single_fw()
374 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; in amdgpu_ucode_init_single_fw()
375 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm, in amdgpu_ucode_init_single_fw()
378 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; in amdgpu_ucode_init_single_fw()
379 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm, in amdgpu_ucode_init_single_fw()
HDgfx_v8_0.c958 kfree(adev->gfx.rlc.register_list_format); in gfx_v8_0_free_microcode()
1087 adev->gfx.rlc.save_and_restore_offset = in gfx_v8_0_init_microcode()
1089 adev->gfx.rlc.clear_state_descriptor_offset = in gfx_v8_0_init_microcode()
1091 adev->gfx.rlc.avail_scratch_ram_locations = in gfx_v8_0_init_microcode()
1093 adev->gfx.rlc.reg_restore_list_size = in gfx_v8_0_init_microcode()
1095 adev->gfx.rlc.reg_list_format_start = in gfx_v8_0_init_microcode()
1097 adev->gfx.rlc.reg_list_format_separate_start = in gfx_v8_0_init_microcode()
1099 adev->gfx.rlc.starting_offsets_start = in gfx_v8_0_init_microcode()
1101 adev->gfx.rlc.reg_list_format_size_bytes = in gfx_v8_0_init_microcode()
1103 adev->gfx.rlc.reg_list_size_bytes = in gfx_v8_0_init_microcode()
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HDamdgpu_ucode.h167 struct rlc_firmware_header_v1_0 rlc; member
HDamdgpu.h904 struct amdgpu_rlc rlc; member
/dragonfly/sys/dev/drm/radeon/
HDevergreen.c4096 if (rdev->rlc.save_restore_obj) { in sumo_rlc_fini()
4097 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); in sumo_rlc_fini()
4100 radeon_bo_unpin(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4101 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4103 radeon_bo_unref(&rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4104 rdev->rlc.save_restore_obj = NULL; in sumo_rlc_fini()
4108 if (rdev->rlc.clear_state_obj) { in sumo_rlc_fini()
4109 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); in sumo_rlc_fini()
4112 radeon_bo_unpin(rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4113 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_fini()
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HDradeon_ucode.h215 struct rlc_firmware_header_v1_0 rlc; member
HDcik.c5844 static void cik_update_rlc(struct radeon_device *rdev, u32 rlc) in cik_update_rlc() argument
5849 if (tmp != rlc) in cik_update_rlc()
5850 WREG32(RLC_CNTL, rlc); in cik_update_rlc()
6466 if (rdev->rlc.cp_table_ptr == NULL) in cik_init_cp_pg_table()
6470 dst_ptr = rdev->rlc.cp_table_ptr; in cik_init_cp_pg_table()
6664 if (rdev->rlc.cs_data) { in cik_init_gfx_cgpg()
6666 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6667 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
6668 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size); in cik_init_gfx_cgpg()
6674 if (rdev->rlc.reg_list) { in cik_init_gfx_cgpg()
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HDsi.c5207 static void si_update_rlc(struct radeon_device *rdev, u32 rlc) in si_update_rlc() argument
5212 if (tmp != rlc) in si_update_rlc()
5213 WREG32(RLC_CNTL, rlc); in si_update_rlc()
5269 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_gfx_cgpg()
5275 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5675 if (rdev->rlc.cs_data == NULL) in si_get_csb_size()
5683 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_size()
5707 if (rdev->rlc.cs_data == NULL) in si_get_csb_buffer()
5719 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_buffer()
5771 … WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
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HDni.c2199 rdev->rlc.reg_list = tn_rlc_save_restore_register_list; in cayman_startup()
2200 rdev->rlc.reg_list_size = in cayman_startup()
2202 rdev->rlc.cs_data = cayman_cs_data; in cayman_startup()
HDradeon.h2421 struct radeon_rlc rlc; member
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
HDvega10_powertune.c943 adev->gfx.rlc.funcs->enter_safe_mode(adev); in vega10_enable_cac_driving_se_didt_config()
968 adev->gfx.rlc.funcs->exit_safe_mode(adev); in vega10_enable_cac_driving_se_didt_config()
977 adev->gfx.rlc.funcs->enter_safe_mode(adev); in vega10_disable_cac_driving_se_didt_config()
981 adev->gfx.rlc.funcs->exit_safe_mode(adev); in vega10_disable_cac_driving_se_didt_config()
994 adev->gfx.rlc.funcs->enter_safe_mode(adev); in vega10_enable_psm_gc_didt_config()
1013 adev->gfx.rlc.funcs->exit_safe_mode(adev); in vega10_enable_psm_gc_didt_config()
1030 adev->gfx.rlc.funcs->enter_safe_mode(adev); in vega10_disable_psm_gc_didt_config()
1034 adev->gfx.rlc.funcs->exit_safe_mode(adev); in vega10_disable_psm_gc_didt_config()
1055 adev->gfx.rlc.funcs->enter_safe_mode(adev); in vega10_enable_se_edc_config()
1076 adev->gfx.rlc.funcs->exit_safe_mode(adev); in vega10_enable_se_edc_config()
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HDsmu7_powertune.c970 adev->gfx.rlc.funcs->enter_safe_mode(adev); in smu7_enable_didt_config()
1017 adev->gfx.rlc.funcs->exit_safe_mode(adev); in smu7_enable_didt_config()
1023 adev->gfx.rlc.funcs->exit_safe_mode(adev); in smu7_enable_didt_config()
1037 adev->gfx.rlc.funcs->enter_safe_mode(adev); in smu7_disable_didt_config()
1049 adev->gfx.rlc.funcs->exit_safe_mode(adev); in smu7_disable_didt_config()
1054 adev->gfx.rlc.funcs->exit_safe_mode(adev); in smu7_disable_didt_config()
/dragonfly/contrib/binutils-2.27/gas/doc/
HDc-z80.texi257 @samp{set @var{b},}, @samp{rl}, @samp{rlc}, @samp{rr}, @samp{rrc},
HDc-z8k.texi372 rlc rd,imm1or2 sllb rbd,imm8 trirb @@rd,@@rs,rbr