Searched refs:smc_state_table (Results 1 – 21 of 21) sorted by relevance
520 smu_data->smc_state_table.LinkLevelCount = in tonga_populate_smc_link_level()690 SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; in tonga_populate_all_graphic_levels()703 &(smu_data->smc_state_table.GraphicsLevel[i])); in tonga_populate_all_graphic_levels()709 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in tonga_populate_all_graphic_levels()713 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in tonga_populate_all_graphic_levels()717 … smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in tonga_populate_all_graphic_levels()720 smu_data->smc_state_table.GraphicsDpmLevelCount = in tonga_populate_all_graphic_levels()731 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = in tonga_populate_all_graphic_levels()761 … smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; in tonga_populate_all_graphic_levels()764 … smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; in tonga_populate_all_graphic_levels()[all …]
502 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in fiji_populate_bapm_parameters_in_dpm_table()859 smu_data->smc_state_table.LinkLevelCount = in fiji_populate_smc_link_level()1029 smu_data->smc_state_table.GraphicsLevel; in fiji_populate_all_graphic_levels()1055 smu_data->smc_state_table.GraphicsDpmLevelCount = in fiji_populate_all_graphic_levels()1244 smu_data->smc_state_table.MemoryLevel; in fiji_populate_all_memory_levels()1269 smu_data->smc_state_table.MemoryDpmLevelCount = in fiji_populate_all_memory_levels()1658 smu_data->smc_state_table.GraphicsBootLevel = level; in fiji_populate_smc_initailial_state()1667 smu_data->smc_state_table.MemoryBootLevel = level; in fiji_populate_smc_initailial_state()1712 smu_data->smc_state_table.ClockStretcherAmount = stretch_amount; in fiji_populate_clock_stretcher_data_table()1716 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |= in fiji_populate_clock_stretcher_data_table()[all …]
428 SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); in polaris10_populate_bapm_parameters_in_dpm_table()786 smu_data->smc_state_table.LinkLevelCount = in polaris10_populate_smc_link_level()844 const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table); in polaris10_calculate_sclk_params()991 smu_data->smc_state_table.GraphicsLevel; in polaris10_populate_all_graphic_levels()998 polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table)); in polaris10_populate_all_graphic_levels()1004 &(smu_data->smc_state_table.GraphicsLevel[i])); in polaris10_populate_all_graphic_levels()1014 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0; in polaris10_populate_all_graphic_levels()1016 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in polaris10_populate_all_graphic_levels()1017 smu_data->smc_state_table.GraphicsDpmLevelCount = in polaris10_populate_all_graphic_levels()1134 smu_data->smc_state_table.MemoryLevel; in polaris10_populate_all_memory_levels()[all …]
481 smu_data->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()491 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()493 smu_data->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()497 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()499 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()718 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in ci_populate_bapm_parameters_in_dpm_table()1013 smu_data->smc_state_table.LinkLevelCount = in ci_populate_smc_link_level()1308 SMU7_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()1317 &(smu_data->smc_state_table.MemoryLevel[i])); in ci_populate_all_memory_levels()1322 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()[all …]
339 smu_data->smc_state_table.UvdBootLevel = 0; in vegam_update_uvd_smc_table()341 smu_data->smc_state_table.UvdBootLevel = in vegam_update_uvd_smc_table()350 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; in vegam_update_uvd_smc_table()360 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); in vegam_update_uvd_smc_table()373 smu_data->smc_state_table.VceBootLevel = in vegam_update_vce_smc_table()376 smu_data->smc_state_table.VceBootLevel = 0; in vegam_update_vce_smc_table()385 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16; in vegam_update_vce_smc_table()392 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); in vegam_update_vce_smc_table()590 smu_data->smc_state_table.LinkLevelCount = in vegam_populate_smc_link_level()723 const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table); in vegam_calculate_sclk_params()[all …]
787 smu_data->smc_state_table.LinkLevelCount = in iceland_populate_smc_link_level()970 SMU71_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; in iceland_populate_all_graphic_levels()983 &(smu_data->smc_state_table.GraphicsLevel[i])); in iceland_populate_all_graphic_levels()989 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in iceland_populate_all_graphic_levels()993 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in iceland_populate_all_graphic_levels()997 … smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in iceland_populate_all_graphic_levels()1000 smu_data->smc_state_table.GraphicsDpmLevelCount = in iceland_populate_all_graphic_levels()1027 … smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; in iceland_populate_all_graphic_levels()1031 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; in iceland_populate_all_graphic_levels()1034 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; in iceland_populate_all_graphic_levels()[all …]
42 struct SMU73_Discrete_DpmTable smc_state_table; member
57 SMU74_Discrete_DpmTable smc_state_table; member
66 SMU75_Discrete_DpmTable smc_state_table; member
62 struct SMU71_Discrete_DpmTable smc_state_table; member
66 struct SMU72_Discrete_DpmTable smc_state_table; member
68 struct SMU7_Discrete_DpmTable smc_state_table; member
929 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega10_setup_dpm_led_config()1437 data->smc_state_table.pp_table.UlvOffsetVid = in vega10_populate_ulv_state()1440 data->smc_state_table.pp_table.UlvSmnclkDid = in vega10_populate_ulv_state()1442 data->smc_state_table.pp_table.UlvMp1clkDid = in vega10_populate_ulv_state()1444 data->smc_state_table.pp_table.UlvGfxclkBypass = in vega10_populate_ulv_state()1446 data->smc_state_table.pp_table.UlvPhaseSheddingPsi0 = in vega10_populate_ulv_state()1448 data->smc_state_table.pp_table.UlvPhaseSheddingPsi1 = in vega10_populate_ulv_state()1475 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega10_populate_smc_link_levels()1633 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega10_populate_all_graphic_levels()1688 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega10_populate_vddc_soc_levels()[all …]
509 PPTable_t *table = &(data->smc_state_table.pp_table); in vega10_thermal_setup_fan_table()553 (uint8_t *)(&(data->smc_state_table.pp_table)), in vega10_thermal_setup_fan_table()
261 PPTable_t *table = &(data->smc_state_table.pp_table); in vega12_thermal_setup_fan_table()
393 struct vega12_smc_state_table smc_state_table; member
380 struct vega10_smc_state_table smc_state_table; member
723 PPTable_t *pp_table = &(data->smc_state_table.pp_table); in vega12_init_smc_table()1780 Watermarks_t *table = &(data->smc_state_table.water_marks_table); in vega12_set_watermarks_for_clocks_ranges()2104 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega12_display_configuration_changed_task()
1294 PPTable_t *table = &(data->smc_state_table.pp_table); in vega10_initialize_power_tune_defaults()
427 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table()1339 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits()2630 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state()2638 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state()2677 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()3318 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()3327 … &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()3331 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()3333 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()3336 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()[all …]
223 SMU7_Discrete_DpmTable smc_state_table; member