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Searched refs:train_set (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/i915/
HDintel_dp_link_training.c64 intel_dp->train_set[lane] = v | p; in intel_get_adjust_train()
71 uint8_t buf[sizeof(intel_dp->train_set) + 1]; in intel_dp_set_link_train()
83 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); in intel_dp_set_link_train()
97 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); in intel_dp_reset_link_train()
110 intel_dp->train_set, intel_dp->lane_count); in intel_dp_update_link_train()
120 if ((intel_dp->train_set[lane] & in intel_dp_link_max_vswing_reached()
195 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in intel_dp_link_training_clock_recovery()
204 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == in intel_dp_link_training_clock_recovery()
HDintel_dp.c3247 uint8_t train_set = intel_dp->train_set[0]; in vlv_signal_levels() local
3249 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in vlv_signal_levels()
3252 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_signal_levels()
3275 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_signal_levels()
3294 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_signal_levels()
3309 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_signal_levels()
3333 uint8_t train_set = intel_dp->train_set[0]; in chv_signal_levels() local
3335 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in chv_signal_levels()
3337 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in chv_signal_levels()
3360 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in chv_signal_levels()
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HDintel_ddi.c2086 uint8_t train_set = intel_dp->train_set[0]; in intel_ddi_dp_level() local
2087 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in intel_ddi_dp_level()
HDintel_drv.h986 uint8_t train_set[4]; member
/dragonfly/sys/dev/drm/amd/amdgpu/
HDatombios_dp.c208 u8 train_set[4]) in amdgpu_atombios_dp_get_adjust_train()
240 train_set[lane] = v | p; in amdgpu_atombios_dp_get_adjust_train()
486 u8 train_set[4]; member
498 … 0, dp_info->train_set[0]); /* sets all lanes at once */ in amdgpu_atombios_dp_update_vs_emph()
502 dp_info->train_set, dp_info->dp_lane_count); in amdgpu_atombios_dp_update_vs_emph()
596 memset(dp_info->train_set, 0, 4); in amdgpu_atombios_dp_link_train_cr()
620 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in amdgpu_atombios_dp_link_train_cr()
628 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in amdgpu_atombios_dp_link_train_cr()
637 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in amdgpu_atombios_dp_link_train_cr()
641 dp_info->train_set); in amdgpu_atombios_dp_link_train_cr()
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/dragonfly/sys/dev/drm/radeon/
HDatombios_dp.c258 u8 train_set[4]) in dp_get_adjust_train()
290 train_set[lane] = v | p; in dp_get_adjust_train()
548 u8 train_set[4]; member
560 … 0, dp_info->train_set[0]); /* sets all lanes at once */ in radeon_dp_update_vs_emph()
564 dp_info->train_set, dp_info->dp_lane_count); in radeon_dp_update_vs_emph()
675 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()
699 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()
707 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in radeon_dp_link_train_cr()
716 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()
719 … dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); in radeon_dp_link_train_cr()
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