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Searched refs:txdctl (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/netif/ig_hal/
HDe1000_82540.c331 u32 txdctl, ctrl_ext; in e1000_init_hw_82540() local
375 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); in e1000_init_hw_82540()
376 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | in e1000_init_hw_82540()
378 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); in e1000_init_hw_82540()
HDe1000_82541.c375 u32 i, txdctl; in e1000_init_hw_82541() local
416 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); in e1000_init_hw_82541()
417 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | in e1000_init_hw_82541()
419 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); in e1000_init_hw_82541()
HDe1000_ich8lan.c5078 u32 ctrl_ext, txdctl, snoop; in e1000_init_hw_ich8lan() local
5117 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); in e1000_init_hw_ich8lan()
5118 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | in e1000_init_hw_ich8lan()
5120 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | in e1000_init_hw_ich8lan()
5122 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); in e1000_init_hw_ich8lan()
5123 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(1)); in e1000_init_hw_ich8lan()
5124 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | in e1000_init_hw_ich8lan()
5126 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | in e1000_init_hw_ich8lan()
5128 E1000_WRITE_REG(hw, E1000_TXDCTL(1), txdctl); in e1000_init_hw_ich8lan()
/dragonfly/sys/dev/netif/emx/
HDif_emx.c2476 uint32_t tctl, tarc, tipg = 0, txdctl; in emx_init_tx_unit() local
2495 txdctl = 0x1f; /* PTHRESH */ in emx_init_tx_unit()
2496 txdctl |= 1 << 8; /* HTHRESH */ in emx_init_tx_unit()
2497 txdctl |= 1 << 16; /* WTHRESH */ in emx_init_tx_unit()
2498 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ in emx_init_tx_unit()
2499 txdctl |= E1000_TXDCTL_GRAN; in emx_init_tx_unit()
2500 txdctl |= 1 << 25; /* LWTHRESH */ in emx_init_tx_unit()
2502 E1000_WRITE_REG(&sc->hw, E1000_TXDCTL(i), txdctl); in emx_init_tx_unit()
2535 txdctl = E1000_READ_REG(&sc->hw, E1000_TXDCTL(0)); in emx_init_tx_unit()
2536 E1000_WRITE_REG(&sc->hw, E1000_TXDCTL(1), txdctl); in emx_init_tx_unit()
/dragonfly/sys/dev/netif/em/
HDif_em.c2984 uint32_t txdctl = 0; in em_init_tx_unit() local
2986 txdctl |= 0x1f; /* PTHRESH */ in em_init_tx_unit()
2987 txdctl |= 1 << 8; /* HTHRESH */ in em_init_tx_unit()
2988 txdctl |= 1 << 16; /* WTHRESH */ in em_init_tx_unit()
2989 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */ in em_init_tx_unit()
2990 txdctl |= E1000_TXDCTL_GRAN; in em_init_tx_unit()
2991 txdctl |= 1 << 25; /* LWTHRESH */ in em_init_tx_unit()
2993 E1000_WRITE_REG(&adapter->hw, E1000_TXDCTL(0), txdctl); in em_init_tx_unit()
/dragonfly/sys/dev/netif/igb/
HDif_igb.c2047 uint32_t txdctl = 0; in igb_init_tx_unit() local
2081 txdctl |= IGB_TX_PTHRESH; in igb_init_tx_unit()
2082 txdctl |= IGB_TX_HTHRESH << 8; in igb_init_tx_unit()
2083 txdctl |= IGB_TX_WTHRESH << 16; in igb_init_tx_unit()
2084 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; in igb_init_tx_unit()
2085 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl); in igb_init_tx_unit()
/dragonfly/sys/dev/netif/ix/
HDif_ix.c997 uint32_t txdctl; in ix_init() local
999 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); in ix_init()
1000 txdctl |= IXGBE_TXDCTL_ENABLE; in ix_init()
1005 txdctl &= ~(0x7f << 16); in ix_init()
1014 txdctl |= (32 << 0) | (1 << 8); in ix_init()
1015 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), txdctl); in ix_init()