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Searched refs:vm_manager (Results 1 – 25 of 29) sorted by relevance

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/dragonfly/sys/dev/drm/amd/amdgpu/
HDamdgpu_vm.c262 adev->vm_manager.block_size; in amdgpu_vm_level_shift()
287 adev->vm_manager.root_level); in amdgpu_vm_num_entries()
289 if (level == adev->vm_manager.root_level) in amdgpu_vm_num_entries()
291 return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift; in amdgpu_vm_num_entries()
441 if (level == adev->vm_manager.root_level) { in amdgpu_vm_clear_bo()
661 if (eaddr >= adev->vm_manager.max_pfn) { in amdgpu_vm_alloc_pts()
663 eaddr, adev->vm_manager.max_pfn); in amdgpu_vm_alloc_pts()
668 adev->vm_manager.root_level, ats); in amdgpu_vm_alloc_pts()
720 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_need_pipeline_sync()
758 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vm_flush()
[all …]
HDamdgpu_ids.c207 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_idle()
230 u64 fence_context = adev->vm_manager.fence_context + ring->idx; in amdgpu_vmid_grab_idle()
231 unsigned seqno = ++adev->vm_manager.seqno[ring->idx]; in amdgpu_vmid_grab_idle()
343 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab_used()
412 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_grab()
475 id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_alloc_reserved()
502 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_free_reserved()
525 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub]; in amdgpu_vmid_reset()
552 &adev->vm_manager.id_mgr[i]; in amdgpu_vmid_reset_all()
572 &adev->vm_manager.id_mgr[i]; in amdgpu_vmid_mgr_init()
[all …]
HDgfxhub_v1_0.c44 + adev->vm_manager.vram_base_offset; in gfxhub_v1_0_init_gart_pt_regs()
87 + adev->vm_manager.vram_base_offset; in gfxhub_v1_0_init_system_aperture_regs()
196 num_level = adev->vm_manager.num_level; in gfxhub_v1_0_setup_vmid_config()
197 block_size = adev->vm_manager.block_size; in gfxhub_v1_0_setup_vmid_config()
233 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
235 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
HDvega10_ih.c279 lockmgr(&adev->vm_manager.pasid_lock, LK_EXCLUSIVE); in vega10_ih_prescreen_iv()
280 vm = idr_find(&adev->vm_manager.pasid_idr, pasid); in vega10_ih_prescreen_iv()
283 lockmgr(&adev->vm_manager.pasid_lock, LK_RELEASE); in vega10_ih_prescreen_iv()
297 lockmgr(&adev->vm_manager.pasid_lock, LK_RELEASE); in vega10_ih_prescreen_iv()
300 lockmgr(&adev->vm_manager.pasid_lock, LK_RELEASE); in vega10_ih_prescreen_iv()
HDmmhub_v1_0.c54 adev->vm_manager.vram_base_offset; in mmhub_v1_0_init_gart_pt_regs()
98 adev->vm_manager.vram_base_offset; in mmhub_v1_0_init_system_aperture_regs()
209 num_level = adev->vm_manager.num_level; in mmhub_v1_0_setup_vmid_config()
210 block_size = adev->vm_manager.block_size; in mmhub_v1_0_setup_vmid_config()
246 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
248 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
HDgmc_v7_0.c568 uint32_t high = adev->vm_manager.max_pfn - in gmc_v7_0_set_prt()
636 field = adev->vm_manager.fragment_size; in gmc_v7_0_gart_enable()
665 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v7_0_gart_enable()
683 adev->vm_manager.block_size - 9); in gmc_v7_0_gart_enable()
1064 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v7_0_sw_init()
1072 adev->vm_manager.vram_base_offset = tmp; in gmc_v7_0_sw_init()
1074 adev->vm_manager.vram_base_offset = 0; in gmc_v7_0_sw_init()
HDgmc_v9_0.c513 *addr = adev->vm_manager.vram_base_offset + *addr - in gmc_v9_0_get_vm_pde()
704 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev); in gmc_v9_0_vram_gtt_location()
864 adev->vm_manager.num_level > 1; in gmc_v9_0_sw_init()
945 adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v9_0_sw_init()
946 adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v9_0_sw_init()
HDgmc_v8_0.c795 uint32_t high = adev->vm_manager.max_pfn - in gmc_v8_0_set_prt()
864 field = adev->vm_manager.fragment_size; in gmc_v8_0_gart_enable()
908 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v8_0_gart_enable()
933 adev->vm_manager.block_size - 9); in gmc_v8_0_gart_enable()
1190 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS; in gmc_v8_0_sw_init()
1198 adev->vm_manager.vram_base_offset = tmp; in gmc_v8_0_sw_init()
1200 adev->vm_manager.vram_base_offset = 0; in gmc_v8_0_sw_init()
HDamdgpu_amdkfd_gfx_v9.c1034 lower_32_bits(adev->vm_manager.max_pfn - 1)); in set_vm_context_page_table_base()
1036 upper_32_bits(adev->vm_manager.max_pfn - 1)); in set_vm_context_page_table_base()
1045 lower_32_bits(adev->vm_manager.max_pfn - 1)); in set_vm_context_page_table_base()
1047 upper_32_bits(adev->vm_manager.max_pfn - 1)); in set_vm_context_page_table_base()
HDsdma_v2_4.c1317 if (adev->vm_manager.vm_pte_funcs == NULL) { in sdma_v2_4_set_vm_pte_funcs()
1318 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; in sdma_v2_4_set_vm_pte_funcs()
1320 adev->vm_manager.vm_pte_rings[i] = in sdma_v2_4_set_vm_pte_funcs()
1323 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; in sdma_v2_4_set_vm_pte_funcs()
HDamdgpu_vm.h49 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
HDsdma_v3_0.c1757 if (adev->vm_manager.vm_pte_funcs == NULL) { in sdma_v3_0_set_vm_pte_funcs()
1758 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; in sdma_v3_0_set_vm_pte_funcs()
1760 adev->vm_manager.vm_pte_rings[i] = in sdma_v3_0_set_vm_pte_funcs()
1763 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; in sdma_v3_0_set_vm_pte_funcs()
HDsdma_v4_0.c1759 if (adev->vm_manager.vm_pte_funcs == NULL) { in sdma_v4_0_set_vm_pte_funcs()
1760 adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs; in sdma_v4_0_set_vm_pte_funcs()
1762 adev->vm_manager.vm_pte_rings[i] = in sdma_v4_0_set_vm_pte_funcs()
1765 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; in sdma_v4_0_set_vm_pte_funcs()
HDamdgpu.h1449 struct amdgpu_vm_manager vm_manager; member
1735 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib…
1736 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->wri…
1737 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_fu…
HDamdgpu_virt.c31 uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT; in amdgpu_csa_vaddr()
HDamdgpu_amdkfd.c160 .gpuvm_size = min(adev->vm_manager.max_pfn in amdgpu_amdkfd_device_init()
HDamdgpu_kms.c602 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; in amdgpu_info_ioctl()
618 … dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE; in amdgpu_info_ioctl()
HDamdgpu_gem.c591 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; in amdgpu_gem_va_ioctl()
HDamdgpu_device.c2354 adev->vm_manager.vm_pte_funcs = NULL; in amdgpu_device_init()
2355 adev->vm_manager.vm_pte_num_rings = 0; in amdgpu_device_init()
/dragonfly/sys/dev/drm/radeon/
HDradeon_vm.c62 return rdev->vm_manager.max_pfn >> radeon_vm_block_size; in radeon_vm_num_pdes()
89 if (!rdev->vm_manager.enabled) { in radeon_vm_manager_init()
94 rdev->vm_manager.enabled = true; in radeon_vm_manager_init()
110 if (!rdev->vm_manager.enabled) in radeon_vm_manager_fini()
114 radeon_fence_unref(&rdev->vm_manager.active[i]); in radeon_vm_manager_fini()
116 rdev->vm_manager.enabled = false; in radeon_vm_manager_fini()
188 vm_id->last_id_use == rdev->vm_manager.active[vm_id->id]) in radeon_vm_grab_id()
195 for (i = 1; i < rdev->vm_manager.nvm; ++i) { in radeon_vm_grab_id()
196 struct radeon_fence *fence = rdev->vm_manager.active[i]; in radeon_vm_grab_id()
215 return rdev->vm_manager.active[choices[i]]; in radeon_vm_grab_id()
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HDni.c1335 rdev->vm_manager.max_pfn - 1); in cayman_pcie_gart_enable()
1337 rdev->vm_manager.saved_table_addr[i]); in cayman_pcie_gart_enable()
1372 rdev->vm_manager.saved_table_addr[i] = RREG32( in cayman_pcie_gart_disable()
2519 rdev->vm_manager.nvm = 8; in cayman_vm_init()
2524 rdev->vm_manager.vram_base_offset = tmp; in cayman_vm_init()
2526 rdev->vm_manager.vram_base_offset = 0; in cayman_vm_init()
HDradeon_gem.c619 if (!rdev->vm_manager.enabled) { in radeon_gem_va_ioctl()
HDradeon_cs.c366 !p->rdev->vm_manager.enabled) { in radeon_cs_parser_init()
HDsi.c4318 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1); in si_pcie_gart_enable()
4326 rdev->vm_manager.saved_table_addr[i]); in si_pcie_gart_enable()
4329 rdev->vm_manager.saved_table_addr[i]); in si_pcie_gart_enable()
4369 rdev->vm_manager.saved_table_addr[i] = RREG32(reg); in si_pcie_gart_disable()
4787 rdev->vm_manager.nvm = 16; in si_vm_init()
4789 rdev->vm_manager.vram_base_offset = 0; in si_vm_init()
HDcik.c5501 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1); in cik_pcie_gart_enable()
5505 rdev->vm_manager.saved_table_addr[i]); in cik_pcie_gart_enable()
5508 rdev->vm_manager.saved_table_addr[i]); in cik_pcie_gart_enable()
5581 rdev->vm_manager.saved_table_addr[i] = RREG32(reg); in cik_pcie_gart_disable()
5653 rdev->vm_manager.nvm = 16; in cik_vm_init()
5658 rdev->vm_manager.vram_base_offset = tmp; in cik_vm_init()
5660 rdev->vm_manager.vram_base_offset = 0; in cik_vm_init()

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