Home
last modified time | relevance | path

Searched refs:CPUs (Results 1 – 25 of 125) sorted by relevance

12345

/freebsd-13-stable/sys/contrib/device-tree/Bindings/arm/cpu-enable-method/
Dal,alpine-smp6 enabling secondary CPUs. To apply to all CPUs, a single
12 Compatible CPUs: "arm,cortex-a15"
33 system fabric, like powering CPUs off.
Dmarvell,berlin-smp6 CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
11 Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
Dnuvoton,npcm750-smp5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
10 Compatible CPUs: "arm,cortex-a9"
/freebsd-13-stable/sys/contrib/device-tree/Bindings/mips/brcm/
Dbrcm,bmips.txt1 * Broadcom MIPS (BMIPS) CPUs
7 - mips-hpt-frequency: This is common to all CPUs in the system so it lives
/freebsd-13-stable/share/examples/perfmon/
HDREADME2 counters on Pentium and Pentium Pro CPUs. See perfmon(4) for a
15 The following options are not implemented on Pentium CPUs:
/freebsd-13-stable/sys/contrib/device-tree/Bindings/arm/
HDcpu-capacity.txt2 ARM CPUs capacity bindings
18 CPU capacity is a number that provides the scheduler information about CPUs
20 (e.g., ARM big.LITTLE systems) or maximum frequency at which CPUs can run
23 capture a first-order approximation of the relative performance of CPUs.
237 [1] ARM Linux Kernel documentation - CPUs bindings
HDcci.txt21 root node (ie from CPUs perspective as per DT standard).
127 (inclusive of CPUs and their cpu nodes).
223 CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
224 CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};
HDspe-pmu.txt12 SPE is only supported on a subset of the CPUs, please consult
HDarm-dsu-pmu.txt18 - cpus : List of phandles for the CPUs connected to this DSU instance.
/freebsd-13-stable/contrib/llvm-project/compiler-rt/lib/scudo/standalone/
HDlinux.cpp162 cpu_set_t CPUs; in getNumberOfCPUs() local
165 if (sched_getaffinity(0, sizeof(cpu_set_t), &CPUs) != 0) in getNumberOfCPUs()
167 return static_cast<u32>(CPU_COUNT(&CPUs)); in getNumberOfCPUs()
/freebsd-13-stable/sys/contrib/device-tree/Bindings/powerpc/fsl/
HDcpus.txt5 Power Architecture CPUs in Freescale SOCs are represented in device trees as
18 Power CPUs. The EREF defines some architecture categories not defined
/freebsd-13-stable/sys/i386/conf/
HDNOTES42 # HTT CPUs should only be used if they are enabled in the BIOS. For
43 # the ACPI case, ACPI only correctly tells us about any HTT CPUs if
44 # they are enabled. However, most HTT systems do not list HTT CPUs
45 # in the MP Table if they are enabled, thus we guess at the HTT CPUs
47 # these CPUs if HTT is disabled. Thus, HTT guessing is only enabled
59 options MPTABLE_FORCE_HTT # Enable HTT CPUs with the MP Table
79 # deleting the specification for CPUs you don't need to use may make
103 # of Cyrix 6x86 and 6x86MX CPUs by setting the NO_LOCK bit of CCR1.
141 # CPU_PPRO2CELERON enables L2 cache of Mendocino Celeron CPUs. This option
143 # Pro BIOSs do not enable L2 cache of Mendocino Celeron CPUs.
[all …]
/freebsd-13-stable/sys/contrib/device-tree/Bindings/cpu/
HDcpu-topology.txt9 In a SMP system, the hierarchy of CPUs is defined through three entities that
10 are used to describe the layout of physical CPUs in the system:
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
33 correspond to physical CPUs and are to be mapped to the hierarchy levels.
48 Usage: Optional - On SMP systems provide CPUs topology to the OS.
154 If a core node is not a leaf node (CPUs supporting SMT) a core node's
/freebsd-13-stable/sys/contrib/device-tree/Bindings/timer/
Dsnps,archs-gfrc.txt1 Synopsys ARC Free Running 64-bit Global Timer for ARC HS CPUs
Dsnps,archs-rtc.txt1 Synopsys ARC Free Running 64-bit Local Timer for ARC HS CPUs
Dsnps,arc-timer.txt2 - Found on all ARC CPUs (ARC700/ARCHS)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86SchedPredicates.td65 // on recent Intel CPUs.
77 // on recent Intel CPUs.
/freebsd-13-stable/lib/libpmc/pmu-events/
HDREADME3 CPUs by their symbolic names rather than raw event codes (see example below).
44 - Set of 'PMU events tables' for all known CPUs in the architecture,
79 1. Several CPUs can support same set of events and hence use a common
/freebsd-13-stable/sys/contrib/device-tree/Bindings/cpufreq/
HDcpufreq-spear.txt6 which share clock across all CPUs.
/freebsd-13-stable/sys/contrib/device-tree/Bindings/clock/
HDclps711x-clock.txt1 * Clock bindings for the Cirrus Logic CLPS711X CPUs
/freebsd-13-stable/contrib/kyua/admin/
HDtravis-build.sh58 -- We do not know how many CPUs the test machine has. However, parallelizing
/freebsd-13-stable/sys/contrib/device-tree/Bindings/mips/img/
HDpistachio.txt14 be probed via CPS, it is not necessary to specify secondary CPUs. Required
/freebsd-13-stable/sys/contrib/device-tree/Bindings/interrupt-controller/
Dbrcm,bcm2836-l1-intc.txt4 events, and SMP IPIs. One of the CPUs may receive interrupts for the
/freebsd-13-stable/sys/contrib/device-tree/Bindings/openrisc/opencores/
HDor1ksim.txt19 be probed via CPS, it is not necessary to specify secondary CPUs. Required
/freebsd-13-stable/sys/contrib/device-tree/Bindings/arm/omap/
HDmpu.txt5 The MPU contain CPUs, GIC, L2 cache and a local PRCM.

12345