Searched refs:A5 (Results 1 – 25 of 50) sorted by relevance
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199 ||[!A2] SHL A4,1,A5:A4 ; lo<<1203 ||[!A2] ADDAH A5,A3,A3 ; hi<<1|lo>>31208 || SHL A4,1,A5:A4 ; lo<<1212 || ADDAH A5,A3,A3 ; hi<<1|lo>>31232 || MV ARG1,A5 ; copy ap238 || LDW *A5++,B6 ; ap[0]245 || LDW *A5++,A9 ; pre-fetch ap[1]268 [A2] LDW *A5++,A9 ; pre-fetch ap[i+1]
160 * p = R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5))))162 * made as "short" as possible: A1 (which is 1/2), A4 and A5170 * [ S*(A1 + S*(A3 + S*A5)) ]280 * p = R+R*R*(A1+R*(A2+R*(A3+R*(A4+R*(A5+R*A6)))))282 * made as "short" as possible: A1 (which is 1/2), A5 and A6290 * [ R + S*(A1 + S*(A3 + S*A5)) ]538 *-- R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5))))540 *--[R+R*S*(A2+S*A4)] + [S*(A1+S*(A3+S*A5))]545 FMOVE.S #:3AB60B70,fp2 ...fp2 IS A5548 FMUL.X fp1,fp2 ...fp2 IS S*A5[all …]
261 *--R' + R'*S*( [A1+T(A3+T(A5+TA7))] + [S(A2+T(A4+TA6))])283 FADD.D SINA5,FP3 ...A5+TA7286 FMUL.X FP1,FP3 ...T(A5+TA7)289 FADD.D SINA3,FP3 ...A3+T(A5+TA7)292 FMUL.X FP3,FP1 ...T(A3+T(A5+TA7))295 FADD.X SINA1,FP1 ...A1+T(A3+T(A5+TA7))298 FADD.X FP2,FP1 ...[A1+T(A3+T(A5+TA7))]+[S(A2+T(A4+TA6))]635 FADD.D SINA5,FP1 ...A5+S(A6+SA7)640 FMUL.X FP0,FP1 ...S(A5+S(A6+SA7))644 FADD.D SINA4,FP1 ...A4+S(A5+S(A6+SA7))[all …]
94 * P = r + r*r*(A1+r*(A2+...+r*A5)).416 FMOVE.D EXPA5,FP2 ...FP2 IS A5419 FMUL.X FP1,FP2 ...FP2 IS S*A5422 FADD.D EXPA3,FP2 ...FP2 IS A3+S*A5425 FMUL.X FP1,FP2 ...FP2 IS S*(A3+S*A5)428 FADD.D EXPA1,FP2 ...FP2 IS A1+S*(A3+S*A5)431 FMUL.X FP1,FP2 ...FP2 IS S*(A1+S*(A3+S*A5))
414 *--U + V*(A1+U*(A2+U*(A3+U*(A4+U*(A5+U*A6))))) WHICH IS415 *--[U + V*(A1+V*(A3+V*A5))] + [U*V*(A2+V*(A4+V*A6))]421 FMUL.D LOGA5,FP2 ...V*A5424 FADD.D LOGA3,FP2 ...A3+V*A5427 FMUL.X FP3,FP2 ...V*(A3+V*A5)430 FADD.D LOGA1,FP2 ...A1+V*(A3+V*A5)434 FMUL.X FP3,FP2 ...V*(A1+V*(A3+V*A5)), FP3 RELEASED437 FADD.X FP2,FP0 ...U+V*(A1+V*(A3+V*A5)), FP2 RELEASED
67 * A5. Add using the carry the 64-bit quantities in d2:d3 and d4:d5128 * A5. Add mul by 8 to mul by 2. D1 contains the digit formed.
81 #define A5 (13) macro
12 32:A5
113 tf->tf_regs[A5] = 0; in setregs()
217 gr[_REG_A5] = frame->f_regs[A5]; in cpu_getmcontext()357 frame->f_regs[A5] = gr[_REG_A5]; in cpu_setmcontext()
856 #define A5 A0+5 macro910 push A51036 adc C4,A4 $ adc C5,A5 $ adc C6,A6 $ adc C7,A71040 rol A4 $ rol A5 $ rol A6 $ rol A71085 #undef A51237 #define A5 A0+5 macro1294 mov A5, A41305 #undef A51763 #define A5 A0+5 macro1864 mov A7,A6 $ mov A6,A5 $ mov A5,A4 $ mov A4,A3[all …]
371 # define A5 A4 macro395 # define A6 A5
147 #define A5 9 macro
5111 fadd.d SINA5(%pc),%fp3 # A5+TA75114 fmul.x %fp1,%fp3 # T(A5+TA7)5117 fadd.d SINA3(%pc),%fp3 # A3+T(A5+TA7)5120 fmul.x %fp3,%fp1 # T(A3+T(A5+TA7))5123 fadd.x SINA1(%pc),%fp1 # A1+T(A3+T(A5+TA7))6794 # p = R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5)))) #6797 # and A5 are single precision; A2 and A3 are double #6805 # [ S*(A1 + S*(A3 + S*A5)) ] #7161 #-- R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5))))7163 #--[R+R*S*(A2+S*A4)] + [S*(A1+S*(A3+S*A5))][all …]
3872 # A5 = xxxxxxxx #3941 # A5 = xxxxxxxx4012 # A5 = xxxxxxxx #4097 # A5 = xxxxxxxx4168 # A5 = xxxxxxxx #4245 # A5 = xxxxxxxx
5217 fadd.d SINA5(%pc),%fp3 # A5+TA75220 fmul.x %fp1,%fp3 # T(A5+TA7)5223 fadd.d SINA3(%pc),%fp3 # A3+T(A5+TA7)5226 fmul.x %fp3,%fp1 # T(A3+T(A5+TA7))5229 fadd.x SINA1(%pc),%fp1 # A1+T(A3+T(A5+TA7))6900 # p = R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5)))) #6903 # and A5 are single precision; A2 and A3 are double #6911 # [ S*(A1 + S*(A3 + S*A5)) ] #7267 #-- R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5))))7269 #--[R+R*S*(A2+S*A4)] + [S*(A1+S*(A3+S*A5))][all …]
147 A0,A1,A2,A3,A4,A5,A6,A7, enumerator
197 a9ptmr* at fdt? pass 2 # ARM Cortex A5/A9 Private Timer199 a9tmr* at fdt? pass 2 # ARM Cortex A5/A9 Timer212 a9wdt* at fdt? pass 2 # ARM Cortex A5/A9 Watchdog
57 C0:C4:1E:26:C8:53:2E:80:A5:50:44:F1:79:38:05:B4:12:CA:AA:7F
1 ;; ARM Cortex-A5 pipeline description
1384 #define HEX_DIGIT_10100101 A5
141 A5. The 1.06 Microsoft initiator silently enforces a chap password
1935 01A4; 01A5; Case map2053 03A5; 03C5; Case map2180 04A4; 04A5; Case map3543 01A4; 01A5; Case map3660 03A5; 03C5; Case map3784 04A4; 04A5; Case map4552 0780-07A5