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Searched refs:AR_PHY_TIMING_CTRL4 (Results 1 – 14 of 14) sorted by relevance

/netbsd/src/sys/external/isc/atheros_hal/dist/ar5212/
Dar5212_reset.c529 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, in ar5212Reset()
532 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, in ar5212Reset()
1005 !(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) { in ar5212PerCalibrationN()
1022 OS_REG_WRITE (ah, AR_PHY_TIMING_CTRL4, in ar5212PerCalibrationN()
1023 OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) | in ar5212PerCalibrationN()
1068 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, in ar5212PerCalibrationN()
1070 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, in ar5212PerCalibrationN()
1072 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, in ar5212PerCalibrationN()
1086 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, in ar5212PerCalibrationN()
1089 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, in ar5212PerCalibrationN()
[all …]
Dar5212phy.h162 #define AR_PHY_TIMING_CTRL4 0x9920 /* timing control */ macro
/netbsd/src/sys/external/isc/atheros_hal/dist/ar5416/
Dar5416_cal.c68 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, in ar5416SetupMeasurement()
96 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_DO_CAL); in ar5416SetupMeasurement()
140 if (!ath_hal_wait(ah, AR_PHY_TIMING_CTRL4, AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {
358 if (!(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_CAL)) { in ar5416DoCalibration()
Dar5416_cal_iq.c130 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, in ar5416IQCalibration()
Dar5416phy.h58 (AR_PHY_TIMING_CTRL4 + ((_i) << 12))
Dar9285_reset.c259 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, in ar9285SetBoardValues()
260 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & in ar9285SetBoardValues()
Dar5416_reset.c1290 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset, in ar5416SetBoardValues()
1291 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) & in ar5416SetBoardValues()
/netbsd/src/sys/external/isc/atheros_hal/dist/ar5211/
Dar5211phy.h54 #define AR_PHY_TIMING_CTRL4 0x9920 /* PHY */ macro
Dar5211_reset.c486 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, in ar5211Reset()
687 !(OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) & AR_PHY_TIMING_CTRL4_DO_IQCAL)) { in ar5211PerCalibrationN()
725 data = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4) | in ar5211PerCalibrationN()
729 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4, data); in ar5211PerCalibrationN()
/netbsd/src/sys/external/isc/atheros_hal/dist/ar5312/
Dar5312_reset.c492 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4, in ar5312Reset()
495 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4, in ar5312Reset()
/netbsd/src/sys/dev/usb/
Dif_otusreg.h213 #define AR_PHY_TIMING_CTRL4 (AR_PHY_BASE + 0x0120) macro
Dif_otus.c2659 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4); in otus_set_board_values()
2662 otus_write(sc, AR_PHY_TIMING_CTRL4, tmp); in otus_set_board_values()
2664 tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4 + offset); in otus_set_board_values()
2667 otus_write(sc, AR_PHY_TIMING_CTRL4 + offset, tmp); in otus_set_board_values()
/netbsd/src/sys/dev/ic/
Darn5008reg.h94 #define AR_PHY_TIMING_CTRL4(i) (0x9920 + (i) * 0x1000) macro
Darn5008.c2078 reg = AR_READ(sc, AR_PHY_TIMING_CTRL4(i)); in ar5008_calib_iq()
2081 AR_WRITE(sc, AR_PHY_TIMING_CTRL4(i), reg); in ar5008_calib_iq()