Searched refs:CMD_PHASE (Results 1 – 16 of 16) sorted by relevance
275 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && in wd33c93_selectbus()368 case SBIC_CSR_XFERRED | CMD_PHASE: in wd33c93_nextstate()369 case SBIC_CSR_MIS | CMD_PHASE: in wd33c93_nextstate()370 case SBIC_CSR_MIS_1 | CMD_PHASE: in wd33c93_nextstate()371 case SBIC_CSR_MIS_2 | CMD_PHASE: in wd33c93_nextstate()
378 #define CMD_PHASE 0x02 macro
520 phase = CMD_PHASE; in sciicmd()533 case CMD_PHASE: in sciicmd()623 phase = CMD_PHASE; in scigo()635 case CMD_PHASE: in scigo()
1043 && csr != (SBIC_CSR_MIS_2|CMD_PHASE) && csr != SBIC_CSR_SEL_TIMEO); in sbicselectbus()1051 if (csr == (SBIC_CSR_MIS_2|CMD_PHASE)) { in sbicselectbus()1164 case CMD_PHASE: in sbicxfstart()1407 case SBIC_CSR_XFERRED|CMD_PHASE: in sbicicmd()1408 case SBIC_CSR_MIS|CMD_PHASE: in sbicicmd()1409 case SBIC_CSR_MIS_1|CMD_PHASE: in sbicicmd()1410 case SBIC_CSR_MIS_2|CMD_PHASE: in sbicicmd()1411 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) in sbicicmd()1413 cbuf, CMD_PHASE)) in sbicicmd()2214 case SBIC_CSR_XFERRED|CMD_PHASE: in sbicnextstate()[all …]
94 #define CMD_PHASE 0x02 macro
169 #define CMD_PHASE 0x02 macro
979 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && in sbicselectbus()988 if (csr == (SBIC_CSR_MIS_2 | CMD_PHASE)) { in sbicselectbus()1097 case CMD_PHASE: in sbicxfstart()1342 case SBIC_CSR_XFERRED | CMD_PHASE: in sbicicmd()1343 case SBIC_CSR_MIS | CMD_PHASE: in sbicicmd()1344 case SBIC_CSR_MIS_1 | CMD_PHASE: in sbicicmd()1345 case SBIC_CSR_MIS_2 | CMD_PHASE: in sbicicmd()1346 if (sbicxfstart(regs, clen, CMD_PHASE, sbic_cmd_wait)) in sbicicmd()1348 cbuf, CMD_PHASE)) in sbicicmd()2040 case SBIC_CSR_XFERRED | CMD_PHASE: in sbicnextstate()[all …]
159 #define CMD_PHASE 0x02 macro
1028 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && in sbicselectbus()1379 case SBIC_CSR_XFERRED | CMD_PHASE: in sbicicmd()1380 case SBIC_CSR_MIS | CMD_PHASE: in sbicicmd()1381 case SBIC_CSR_MIS_1 | CMD_PHASE: in sbicicmd()1382 case SBIC_CSR_MIS_2 | CMD_PHASE: in sbicicmd()2108 case SBIC_CSR_XFERRED | CMD_PHASE: in sbicnextstate()2109 case SBIC_CSR_MIS | CMD_PHASE: in sbicnextstate()2110 case SBIC_CSR_MIS_1 | CMD_PHASE: in sbicnextstate()2111 case SBIC_CSR_MIS_2 | CMD_PHASE: in sbicnextstate()
156 #define CMD_PHASE 0x02 macro
284 phase = CMD_PHASE; in scsiicmd()289 case CMD_PHASE: in scsiicmd()
147 #define CMD_PHASE 0x02 macro
123 #define CMD_PHASE 0x02 macro
760 } else if (hs->sc_phase == CMD_PHASE) { in scintr()
1051 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && in wd33c93_selectbus()1898 case SBIC_CSR_XFERRED | CMD_PHASE: in wd33c93_nextstate()1899 case SBIC_CSR_MIS | CMD_PHASE: in wd33c93_nextstate()1900 case SBIC_CSR_MIS_1 | CMD_PHASE: in wd33c93_nextstate()1901 case SBIC_CSR_MIS_2 | CMD_PHASE: in wd33c93_nextstate()2349 case CMD_PHASE: in wd33c93_print_csr()
353 #define CMD_PHASE 0x02 macro