| /netbsd/src/sys/arch/hpc/conf/ |
| D | platid.def | 37 * CPU definitions
39 CPU:
100 CPU=MIPS_VR_4102 11 -"11" 12 -"12" 13 -"13"
104 CPU=MIPS_VR_41XX
106 CPU=MIPS_VR_4111 300 -"300"
107 CPU=MIPS_VR_4121 320 -"320"
108 CPU=MIPS_VR_4111 forDoCoMo --" MobileGearII for DoCoMo"
109 CPU=MIPS_VR_4102 mpro700 --" MobilePro 700"
110 CPU=MIPS_VR_4121 330 -"330"
113 CPU=MIPS_VR_4111 500 -"500"
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| /netbsd/src/external/gpl3/gdb/dist/sim/m32r/ |
| D | m32r2.c | 57 return (((CPU (h_bpsw) & 0xc1) << 8) in m32r2f_h_cr_get_handler()
58 | ((CPU (h_psw) & 0xc0) << 0) in m32r2f_h_cr_get_handler()
61 return CPU (h_bbpsw) & 0xc1; in m32r2f_h_cr_get_handler()
66 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler()
68 return CPU (h_cr[H_CR_SPI]); in m32r2f_h_cr_get_handler()
71 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler()
73 return CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_get_handler()
75 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe; in m32r2f_h_cr_get_handler()
77 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe; in m32r2f_h_cr_get_handler()
80 return CPU (h_cr[cr]); in m32r2f_h_cr_get_handler()
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| D | m32rx.c | 57 return (((CPU (h_bpsw) & 0xc1) << 8) in m32rxf_h_cr_get_handler()
58 | ((CPU (h_psw) & 0xc0) << 0) in m32rxf_h_cr_get_handler()
61 return CPU (h_bbpsw) & 0xc1; in m32rxf_h_cr_get_handler()
66 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler()
68 return CPU (h_cr[H_CR_SPI]); in m32rxf_h_cr_get_handler()
71 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler()
73 return CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_get_handler()
75 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe; in m32rxf_h_cr_get_handler()
77 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe; in m32rxf_h_cr_get_handler()
80 return CPU (h_cr[cr]); in m32rxf_h_cr_get_handler()
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| D | m32r.c | 155 return (((CPU (h_bpsw) & 0xc1) << 8) in m32rbf_h_cr_get_handler()
156 | ((CPU (h_psw) & 0xc0) << 0) in m32rbf_h_cr_get_handler()
159 return CPU (h_bbpsw) & 0xc1; in m32rbf_h_cr_get_handler()
164 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler()
166 return CPU (h_cr[H_CR_SPI]); in m32rbf_h_cr_get_handler()
169 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler()
171 return CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_get_handler()
173 return CPU (h_cr[H_CR_BPC]) & 0xfffffffe; in m32rbf_h_cr_get_handler()
175 return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe; in m32rbf_h_cr_get_handler()
178 return CPU (h_cr[cr]); in m32rbf_h_cr_get_handler()
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| D | cpu.c | 36 return CPU (h_pc); in m32rbf_h_pc_get()
44 CPU (h_pc) = newval; in m32rbf_h_pc_set()
52 return CPU (h_gr[regno]); in m32rbf_h_gr_get()
60 CPU (h_gr[regno]) = newval; in m32rbf_h_gr_set()
100 return CPU (h_cond); in m32rbf_h_cond_get()
108 CPU (h_cond) = newval; in m32rbf_h_cond_set()
132 return CPU (h_bpsw); in m32rbf_h_bpsw_get()
140 CPU (h_bpsw) = newval; in m32rbf_h_bpsw_set()
148 return CPU (h_bbpsw); in m32rbf_h_bbpsw_get()
156 CPU (h_bbpsw) = newval; in m32rbf_h_bbpsw_set()
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| D | cpu2.c | 36 return CPU (h_pc); in m32r2f_h_pc_get()
44 CPU (h_pc) = newval; in m32r2f_h_pc_set()
52 return CPU (h_gr[regno]); in m32r2f_h_gr_get()
60 CPU (h_gr[regno]) = newval; in m32r2f_h_gr_set()
116 return CPU (h_cond); in m32r2f_h_cond_get()
124 CPU (h_cond) = newval; in m32r2f_h_cond_set()
148 return CPU (h_bpsw); in m32r2f_h_bpsw_get()
156 CPU (h_bpsw) = newval; in m32r2f_h_bpsw_set()
164 return CPU (h_bbpsw); in m32r2f_h_bbpsw_get()
172 CPU (h_bbpsw) = newval; in m32r2f_h_bbpsw_set()
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| D | cpux.c | 36 return CPU (h_pc); in m32rxf_h_pc_get()
44 CPU (h_pc) = newval; in m32rxf_h_pc_set()
52 return CPU (h_gr[regno]); in m32rxf_h_gr_get()
60 CPU (h_gr[regno]) = newval; in m32rxf_h_gr_set()
116 return CPU (h_cond); in m32rxf_h_cond_get()
124 CPU (h_cond) = newval; in m32rxf_h_cond_set()
148 return CPU (h_bpsw); in m32rxf_h_bpsw_get()
156 CPU (h_bpsw) = newval; in m32rxf_h_bpsw_set()
164 return CPU (h_bbpsw); in m32rxf_h_bbpsw_get()
172 CPU (h_bbpsw) = newval; in m32rxf_h_bbpsw_set()
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| /netbsd/src/external/gpl3/gdb/dist/sim/frv/ |
| D | cpu.c | 36 return CPU (h_reloc_ann); in frvbf_h_reloc_ann_get()
44 CPU (h_reloc_ann) = newval; in frvbf_h_reloc_ann_set()
52 return CPU (h_pc); in frvbf_h_pc_get()
60 CPU (h_pc) = newval; in frvbf_h_pc_set()
68 return CPU (h_psr_imple); in frvbf_h_psr_imple_get()
76 CPU (h_psr_imple) = newval; in frvbf_h_psr_imple_set()
84 return CPU (h_psr_ver); in frvbf_h_psr_ver_get()
92 CPU (h_psr_ver) = newval; in frvbf_h_psr_ver_set()
100 return CPU (h_psr_ice); in frvbf_h_psr_ice_get()
108 CPU (h_psr_ice) = newval; in frvbf_h_psr_ice_set()
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| /netbsd/src/external/gpl3/gdb/dist/opcodes/ |
| D | arc-ext-tbl.h | 58 #define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \ argument
59 { NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \
61 { NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \
63 { NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \
65 { NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \
67 { NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \
69 { NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \
72 #define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ argument
73 EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FLAGS_F)
76 #define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ argument
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| /netbsd/src/external/gpl3/binutils/dist/opcodes/ |
| D | arc-ext-tbl.h | 58 #define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \ argument
59 { NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \
61 { NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \
63 { NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \
65 { NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \
67 { NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \
69 { NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \
72 #define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ argument
73 EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FLAGS_F)
76 #define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \ argument
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| /netbsd/src/external/gpl3/gdb/dist/sim/cris/ |
| D | semcrisv10f-switch.c | 455 CPU (h_xbit) = opval; in CASE()
493 CPU (h_nbit) = opval; in CASE()
497 BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); in CASE()
498 CPU (h_zbit) = opval; in CASE()
506 CPU (h_xbit) = opval; in CASE()
546 CPU (h_nbit) = opval; in CASE()
550 BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); in CASE()
551 CPU (h_zbit) = opval; in CASE()
559 CPU (h_xbit) = opval; in CASE()
595 CPU (h_nbit) = opval; in CASE()
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| D | semcrisv32f-switch.c | 471 CPU (h_nbit) = opval; in CASE()
475 BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); in CASE()
476 CPU (h_zbit) = opval; in CASE()
484 CPU (h_xbit) = opval; in CASE()
524 CPU (h_nbit) = opval; in CASE()
528 BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); in CASE()
529 CPU (h_zbit) = opval; in CASE()
537 CPU (h_xbit) = opval; in CASE()
573 CPU (h_nbit) = opval; in CASE()
577 BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); in CASE()
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| D | cpuv32.c | 52 return CPU (h_pc); in crisv32f_h_pc_get()
84 return CPU (h_gr_acr[regno]); in crisv32f_h_gr_acr_get()
92 CPU (h_gr_acr[regno]) = newval; in crisv32f_h_gr_acr_set()
164 return CPU (h_cbit); in crisv32f_h_cbit_get()
172 CPU (h_cbit) = newval; in crisv32f_h_cbit_set()
212 return CPU (h_vbit); in crisv32f_h_vbit_get()
220 CPU (h_vbit) = newval; in crisv32f_h_vbit_set()
260 return CPU (h_zbit); in crisv32f_h_zbit_get()
268 CPU (h_zbit) = newval; in crisv32f_h_zbit_set()
308 return CPU (h_nbit); in crisv32f_h_nbit_get()
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| D | cpuv10.c | 52 return CPU (h_pc); in crisv10f_h_pc_get()
100 return CPU (h_gr_real_pc[regno]); in crisv10f_h_gr_real_pc_get()
108 CPU (h_gr_real_pc[regno]) = newval; in crisv10f_h_gr_real_pc_set()
164 return CPU (h_cbit); in crisv10f_h_cbit_get()
172 CPU (h_cbit) = newval; in crisv10f_h_cbit_set()
212 return CPU (h_vbit); in crisv10f_h_vbit_get()
220 CPU (h_vbit) = newval; in crisv10f_h_vbit_set()
260 return CPU (h_zbit); in crisv10f_h_zbit_get()
268 CPU (h_zbit) = newval; in crisv10f_h_zbit_set()
308 return CPU (h_nbit); in crisv10f_h_nbit_get()
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| D | cpuv32.h | 47 #define GET_H_PC() CPU (h_pc)
50 CPU (h_pc) = ANDSI ((x), (~ (1)));\
54 #define GET_H_GR_ACR(a1) CPU (h_gr_acr)[a1]
55 #define SET_H_GR_ACR(a1, x) (CPU (h_gr_acr)[a1] = (x))
58 …CPU (h_sr_v32[((UINT) 13)]), 1073740800), ORSI (ZEXTBISI (CPU (h_cbit)), ORSI (SLLSI (ZEXTBISI (CP…
66 CPU (h_cbit) = ((NESI (ANDSI ((x), ((1) << (0))), 0)) ? (1) : (0));\
67 CPU (h_vbit) = ((NESI (ANDSI ((x), ((1) << (1))), 0)) ? (1) : (0));\
68 CPU (h_zbit) = ((NESI (ANDSI ((x), ((1) << (2))), 0)) ? (1) : (0));\
69 CPU (h_nbit) = ((NESI (ANDSI ((x), ((1) << (3))), 0)) ? (1) : (0));\
70 CPU (h_xbit) = ((NESI (ANDSI ((x), ((1) << (4))), 0)) ? (1) : (0));\
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| D | cpuv10.h | 47 #define GET_H_PC() CPU (h_pc)
50 CPU (h_pc) = ANDSI ((x), (~ (1)));\
54 #define GET_H_GR_REAL_PC(a1) CPU (h_gr_real_pc)[a1]
55 #define SET_H_GR_REAL_PC(a1, x) (CPU (h_gr_real_pc)[a1] = (x))
58 …CPU (h_sr_v10[((UINT) 5)]), 0xffffff00), ORSI (ZEXTBISI (CPU (h_cbit)), ORSI (SLLSI (ZEXTBISI (CPU…
66 CPU (h_cbit) = ((NESI (ANDSI ((x), ((1) << (0))), 0)) ? (1) : (0));\
67 CPU (h_vbit) = ((NESI (ANDSI ((x), ((1) << (1))), 0)) ? (1) : (0));\
68 CPU (h_zbit) = ((NESI (ANDSI ((x), ((1) << (2))), 0)) ? (1) : (0));\
69 CPU (h_nbit) = ((NESI (ANDSI ((x), ((1) << (3))), 0)) ? (1) : (0));\
70 CPU (h_xbit) = ((NESI (ANDSI ((x), ((1) << (4))), 0)) ? (1) : (0));\
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| /netbsd/src/external/gpl3/gdb/dist/sim/lm32/ |
| D | sem-switch.c | 312 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); in CASE()
313 CPU (h_gr[FLD (f_r2)]) = opval; in CASE()
331 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))); in CASE()
332 CPU (h_gr[FLD (f_r1)]) = opval; in CASE()
350 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); in CASE()
351 CPU (h_gr[FLD (f_r2)]) = opval; in CASE()
369 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))); in CASE()
370 CPU (h_gr[FLD (f_r1)]) = opval; in CASE()
388 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16)); in CASE()
389 CPU (h_gr[FLD (f_r1)]) = opval; in CASE()
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| D | sem.c | 212 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); in SEM_FN_NAME()
213 CPU (h_gr[FLD (f_r2)]) = opval; in SEM_FN_NAME()
233 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))); in SEM_FN_NAME()
234 CPU (h_gr[FLD (f_r1)]) = opval; in SEM_FN_NAME()
254 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); in SEM_FN_NAME()
255 CPU (h_gr[FLD (f_r2)]) = opval; in SEM_FN_NAME()
275 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))); in SEM_FN_NAME()
276 CPU (h_gr[FLD (f_r1)]) = opval; in SEM_FN_NAME()
296 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16)); in SEM_FN_NAME()
297 CPU (h_gr[FLD (f_r1)]) = opval; in SEM_FN_NAME()
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| /netbsd/src/external/gpl3/gdb/dist/sim/mn10300/ |
| D | am33-2.igen | 140 fpu_disabled_exception (SD, CPU, cia);
156 fpu_disabled_exception (SD, CPU, cia);
173 fpu_disabled_exception (SD, CPU, cia);
189 fpu_disabled_exception (SD, CPU, cia);
205 fpu_disabled_exception (SD, CPU, cia);
221 fpu_disabled_exception (SD, CPU, cia);
238 fpu_disabled_exception (SD, CPU, cia);
254 fpu_disabled_exception (SD, CPU, cia);
270 fpu_disabled_exception (SD, CPU, cia);
283 fpu_disabled_exception (SD, CPU, cia);
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| /netbsd/src/external/gpl3/gdb/dist/sim/mips/ |
| D | sim-main.c | 53 sim_cpu *CPU, in load_memory() argument
84 …dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLengt… in load_memory()
94 unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr); in load_memory()
100 value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr); in load_memory()
103 value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr); in load_memory()
106 value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr); in load_memory()
109 value = sim_core_read_misaligned_5 (CPU, cia, read_map, pAddr); in load_memory()
112 value = sim_core_read_aligned_4 (CPU, cia, read_map, pAddr); in load_memory()
115 value = sim_core_read_misaligned_3 (CPU, cia, read_map, pAddr); in load_memory()
118 value = sim_core_read_aligned_2 (CPU, cia, read_map, pAddr); in load_memory()
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| D | sim-main.h | 23 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ argument
24 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
173 #define PENDING_IN (MIPS_SIM_CPU (CPU)->pending.in)
174 #define PENDING_OUT (MIPS_SIM_CPU (CPU)->pending.out)
175 #define PENDING_TOTAL (MIPS_SIM_CPU (CPU)->pending.total)
176 #define PENDING_SLOT_SIZE (MIPS_SIM_CPU (CPU)->pending.slot_size)
177 #define PENDING_SLOT_BIT (MIPS_SIM_CPU (CPU)->pending.slot_bit)
178 #define PENDING_SLOT_DELAY (MIPS_SIM_CPU (CPU)->pending.slot_delay)
179 #define PENDING_SLOT_DEST (MIPS_SIM_CPU (CPU)->pending.slot_dest)
180 #define PENDING_SLOT_VALUE (MIPS_SIM_CPU (CPU)->pending.slot_value)
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| /netbsd/src/external/gpl3/gdb/dist/sim/common/ |
| D | sim-trace.h | 516 if (TRACE_ALU_P (CPU)) \
517 trace_input0 (SD, CPU, TRACE_ALU_IDX); \
522 if (TRACE_ALU_P (CPU)) \
523 trace_input_word1 (SD, CPU, TRACE_ALU_IDX, (V0)); \
528 if (TRACE_ALU_P (CPU)) \
529 trace_input_word2 (SD, CPU, TRACE_ALU_IDX, (V0), (V1)); \
534 if (TRACE_ALU_P (CPU)) \
535 trace_input_word3 (SD, CPU, TRACE_ALU_IDX, (V0), (V1), (V2)); \
540 if (TRACE_ALU_P (CPU)) \
541 trace_input_word4 (SD, CPU, TRACE_ALU_IDX, (V0), (V1), (V2), (V3)); \
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| /netbsd/src/external/gpl3/gdb/dist/sim/microblaze/ |
| D | interp.c | 107 CPU.regs[i] = 0; in set_initial_gprs()
108 CPU.insts = 0; in set_initial_gprs()
109 CPU.cycles = 0; in set_initial_gprs()
110 CPU.imm_enable = 0; in set_initial_gprs()
189 CPU.regs[0] = 0; in sim_engine_run()
279 CPU.regs[0] = 0; in sim_engine_run()
290 RETREG = sim_syscall (cpu, CPU.regs[12], CPU.regs[5], in sim_engine_run()
291 CPU.regs[6], CPU.regs[7], in sim_engine_run()
292 CPU.regs[8]); in sim_engine_run()
311 CPU.insts += insts; /* instructions done ... */ in sim_engine_run()
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| D | microblaze.h | 27 #define CPU (*MICROBLAZE_SIM_CPU (cpu)) macro
29 #define RD CPU.regs[rd]
30 #define RA CPU.regs[ra]
31 #define RB CPU.regs[rb]
34 #define SA CPU.spregs[IMM & 0x1]
36 #define IMM_H CPU.imm_high
39 #define IMM_ENABLE CPU.imm_enable
49 #define PC CPU.spregs[0]
50 #define MSR CPU.spregs[1]
51 #define SP CPU.regs[29]
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| /netbsd/src/external/gpl3/gdb/dist/sim/v850/ |
| D | v850-sim.h | 91 #define GR (V850_SIM_CPU (CPU)->reg.regs)
92 #define SR (V850_SIM_CPU (CPU)->reg.sregs)
93 #define VR (V850_SIM_CPU (CPU)->reg.vregs)
94 #define MPU0_SR (V850_SIM_CPU (CPU)->reg.mpu0_sregs)
95 #define MPU1_SR (V850_SIM_CPU (CPU)->reg.mpu1_sregs)
96 #define FPU_SR (V850_SIM_CPU (CPU)->reg.fpu_sregs)
379 sim_core_read_aligned_2 (CPU, PC, exec_map, (EA))
449 if (TRACE_BRANCH_P (CPU)) { \
460 if (TRACE_BRANCH_P (CPU)) { \
472 if (TRACE_BRANCH_P (CPU)) { \
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