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Searched refs:FGR (Results 1 – 7 of 7) sorted by relevance

/netbsd/src/external/gpl3/gdb/dist/sim/mips/
Dmips3264r6.igen341 TRACE_ALU_INPUT1 (FGR[FT]);
342 if ((FGR[FT] & 0x01) == 0)
353 TRACE_ALU_INPUT1 (FGR[FT]);
354 if ((FGR[FT] & 0x01) != 0)
366 TRACE_ALU_INPUT3 (FGR[FD], FGR[FS], FGR[FT]);
370 TRACE_ALU_RESULT (FGR[FD]);
382 TRACE_ALU_INPUT3 (FGR[FD], FGR[FS], FGR[FT]);
386 TRACE_ALU_RESULT (FGR[FD]);
569 TRACE_ALU_INPUT1 (FGR[FS]);
572 TRACE_ALU_RESULT (FGR[FD]);
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Dcp1.c145 && (FGR[fpr] == 0 || FGR[fpr] == 0xFFFFFFFF))) in value_fpr()
175 value = (FGR[fpr] & 0xFFFFFFFF); in value_fpr()
183 value = FGR[fpr]; in value_fpr()
198 value = (FGR[fpr] & 0xFFFFFFFF); in value_fpr()
210 fpr + 1, pr_uword64 ((uword64) FGR[fpr+1]), in value_fpr()
211 fpr, pr_uword64 ((uword64) FGR[fpr])); in value_fpr()
213 value = ((((uword64) FGR[fpr+1]) << 32) in value_fpr()
214 | (FGR[fpr] & 0xFFFFFFFF)); in value_fpr()
272 FGR[fpr] = (((uword64) 0xDEADC0DE << 32) | (value & 0xFFFFFFFF)); in store_fpr()
283 FGR[fpr] = value; in store_fpr()
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Dmips3264r2.igen111 GPR[rt] = EXTEND32 (WORD64HI (FGR[fs]));
113 GPR[rt] = EXTEND32 (FGR[fs + 1]);
129 StoreFPR (fs, fmt_uninterpreted_64, SET64HI (GPR[rt]) | VL4_8 (FGR[fs]));
Dinterp.c1667 FGR[0] = WORD64LO (GPR[4]); in mips16_entry()
1672 FGR[0] = WORD64LO (GPR[5]); in mips16_entry()
1673 FGR[1] = WORD64LO (GPR[4]); in mips16_entry()
Dsim-main.h226 PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1); \
442 #define FGR (MIPS_SIM_CPU (CPU)->fgr) macro
Dmips.igen1448 GPR[rt] = FGR[fs];
1450 GPR[rt] = SET64HI (FGR[fs+1]) | FGR[fs];
1529 GPR[rt] = EXTEND32 (FGR[fs]);
5780 v = FGR[FS];
5782 v = SET64HI (FGR[FS+1]) | FGR[FS];
6008 v = EXTEND32 (FGR[FS]);
DChangeLog-20211476 (NR_FGR, FGR): Likewise.
2770 FGR from correct location.
2771 (sim_open): Set size of FGR's according to
2774 * sim-main.h (FGR): Store floating point registers in a separate