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Searched refs:GPR (Results 1 – 25 of 183) sorted by relevance

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/netbsd/src/external/gpl3/gcc/dist/gcc/config/rs6000/
Dfusion.md238 (clobber (match_scratch:GPR 0 "=r"))]
245 [(set (match_dup 0) (sign_extend:GPR (match_dup 1)))
259 (clobber (match_scratch:GPR 0 "=r"))]
266 [(set (match_dup 0) (zero_extend:GPR (match_dup 1)))
322 (clobber (match_scratch:GPR 0 "=r"))]
329 [(set (match_dup 0) (zero_extend:GPR (match_dup 1)))
338 ;; load mode is QI result mode is GPR compare mode is CCUNS extend is zero
343 (set (match_operand:GPR 0 "gpc_reg_operand" "=r") (zero_extend:GPR (match_dup 1)))]
350 [(set (match_dup 0) (zero_extend:GPR (match_dup 1)))
362 [(set (match_operand:GPR 3 "gpc_reg_operand" "=&0,&1,&r,r")
[all …]
Drs6000.md458 ; This mode iterator allows :GPR to be used to indicate the allowable size
460 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
486 ; QImode, HImode, SImode for fused ops only for GPR loads
500 ; PTImode is GPR only)
1822 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r")
1823 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b,b")
1824 (match_operand:GPR 2 "add_operand" "r,I,L,eI")))]
1844 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
1845 (match_operand:GPR 2 "gpc_reg_operand" "r,r"))
1847 (clobber (match_scratch:GPR 0 "=r,r"))]
[all …]
Dhtm.md81 (match_operand:GPR 1 "gpc_reg_operand" "r")
82 (match_operand:GPR 2 "gpc_reg_operand" "r")]
94 (match_operand:GPR 1 "gpc_reg_operand" "r")
95 (match_operand:GPR 2 "gpc_reg_operand" "r")]
106 (match_operand:GPR 1 "gpc_reg_operand" "r")
119 (match_operand:GPR 1 "gpc_reg_operand" "r")
269 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
270 (unspec_volatile:GPR [(match_operand 1 "u10bit_cint_operand" "n")]
277 [(unspec_volatile [(match_operand:GPR 0 "gpc_reg_operand" "r")
/netbsd/src/external/gpl3/gdb/dist/sim/mips/
Dmips3264r6.igen23 if (GPR[RS] == 0)
34 NIA = GPR[RT] + (EXTEND16(OFFSET) << 2);
42 if (GPR[RS] != 0)
54 NIA = GPR[RT] + EXTEND16(OFFSET);
67 if ((signed_word)GPR[RT] <= 0)
75 if ((signed_word)GPR[RT] >= 0)
83 if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
100 if ((signed_word)GPR[RT] > 0)
108 if ((signed_word)GPR[RT] < 0)
116 if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
[all …]
Dmips3264r2.igen25 TRACE_ALU_INPUT1 (GPR[rt]);
26 u.d = GPR[rt];
31 GPR[rd] = u.d;
32 TRACE_ALU_RESULT1 (GPR[rd]);
38 TRACE_ALU_INPUT1 (GPR[rt]);
39 d = GPR[rt];
40 GPR[rd] = ((d >> 48)
44 TRACE_ALU_RESULT1 (GPR[rd]);
49 TRACE_ALU_INPUT3 (GPR[rs], lsb, size);
50 GPR[rt] = EXTRACTED64 (GPR[rs], lsb + size, lsb);
[all …]
Dm16e.igen28 TRACE_ALU_INPUT1 (GPR[TRX]);
29 GPR[TRX] = EXTEND8 (GPR[TRX]);
30 TRACE_ALU_RESULT (GPR[TRX]);
38 TRACE_ALU_INPUT1 (GPR[TRX]);
39 GPR[TRX] = EXTEND16 (GPR[TRX]);
40 TRACE_ALU_RESULT (GPR[TRX]);
48 TRACE_ALU_INPUT1 (GPR[TRX]);
49 GPR[TRX] = EXTEND32 (GPR[TRX]);
50 TRACE_ALU_RESULT (GPR[TRX]);
57 TRACE_ALU_INPUT1 (GPR[TRX]);
[all …]
Dmips.igen591 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
593 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
595 ALU32_BEGIN (GPR[rs]);
596 ALU32_ADD (GPR[rt]);
597 ALU32_END (GPR[rd]); /* This checks for overflow. */
599 TRACE_ALU_RESULT (GPR[rd]);
604 if (NotWordValue (GPR[rs]))
606 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
608 ALU32_BEGIN (GPR[rs]);
610 ALU32_END (GPR[rt]); /* This checks for overflow. */
[all …]
Dsmartmips.igen27 GPR[RD] = EXTEND32 (do_load(SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]<<2));
39 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
42 rs = GPR[RS];
43 rt = GPR[RT];
63 GPR[RD] = LO;
67 TRACE_ALU_RESULT4 (ACX,HI,LO,GPR[RD]);
75 TRACE_ALU_INPUT3 (HI,LO,GPR[RS]);
78 LO = GPR[RS];
79 TRACE_ALU_RESULT4 (ACX,HI,LO,GPR[RS]);
90 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
[all …]
Ddsp.igen30 uint32_t v1 = GPR[rs];
31 uint32_t v2 = GPR[rt];
59 GPR[rd] = EXTEND32 (result);
67 uint32_t v1 = GPR[rs];
68 uint32_t v2 = GPR[rt];
83 GPR[rd] = EXTEND32 (h0);
93 uint32_t v1 = GPR[rs];
94 uint32_t v2 = GPR[rt];
117 GPR[rd] = EXTEND32 (result);
125 uint32_t v1 = GPR[rt];
[all …]
Dm16.igen38 GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED));
46 GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE)));
56 GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED);
64 GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE));
74 GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1));
82 GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
92 GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1);
100 GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
110 GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2));
118 GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
[all …]
Dtx.igen12 + ((int64_t) EXTEND32 (GPR[RT])
13 * (int64_t) EXTEND32 (GPR[RS])));
15 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
20 GPR[RD] = LO;
30 + ((uint64_t) VL4_8 (GPR[RS])
31 * (uint64_t) VL4_8 (GPR[RT])));
33 TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
38 GPR[RD] = LO;
Dmicromips.igen70 GPR[rt] = (nia + delayslot_instruction_size) | ISA_MODE_MICROMIPS;
72 delayslot_micromips (SD_, GPR[rs], nia, delayslot_instruction_size)));
247 if (GPR[TRS] == 0)
258 if (GPR[TRS] != 0)
297 delayslot_micromips (SD_, GPR[RS], NIA, MICROMIPS_DELAYSLOT_SIZE_ANY));
317 NIA = process_isa_mode (SD_, GPR[RS]);
330 GPR[TRT] = do_load (SD_, AccessLength_BYTE, GPR[TBASE] + IMM_DEC5, 0);
339 GPR[TRT] = do_load (SD_, AccessLength_HALFWORD, GPR[TBASE], IMM_SHIFT_1BIT);
348 GPR[TRD] = IMM_DEC6;
357 GPR[TRT] = EXTEND32 (
[all …]
Ddsp2.igen31 uint32_t v1 = GPR[rs];
32 uint32_t v2 = GPR[rt];
56 GPR[rd] = EXTEND32 (result);
66 uint32_t v1 = GPR[rs];
67 uint32_t v2 = GPR[rt];
83 GPR[rd] = EXTEND32 (result);
90 uint32_t v1 = GPR[rs];
91 uint32_t v2 = GPR[rt];
117 GPR[rd] = EXTEND32 (result);
124 uint32_t v1 = GPR[rs];
[all …]
Dvr.igen24 // LHS (+/-) GPR[RS] * GPR[RT]
48 x = GPR[rs];
49 y = GPR[rt];
100 GPR[rd] = store_hi_p ? HI : LO;
227 (GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0));
236 (GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0,
Dinterp.c1623 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]); in mips16_entry()
1637 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]); in mips16_entry()
1658 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp); in mips16_entry()
1667 FGR[0] = WORD64LO (GPR[4]); in mips16_entry()
1672 FGR[0] = WORD64LO (GPR[5]); in mips16_entry()
1673 FGR[1] = WORD64LO (GPR[4]); in mips16_entry()
2261 GPR[rt] = (signed_word) (signed_address) COP0_BADVADDR; in decode_coproc()
2263 COP0_BADVADDR = GPR[rt]; in decode_coproc()
2269 GPR[rt] = SR; in decode_coproc()
2271 SR = GPR[rt]; in decode_coproc()
[all …]
/netbsd/src/external/gpl3/gcc/dist/gcc/config/mips/
Dsync.md61 [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
62 (match_operand:GPR 1 "memory_operand" "+ZC,ZC"))
64 (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "dJ,dJ")
65 (match_operand:GPR 3 "arith_operand" "I,d")]
109 [(set (match_operand:GPR 0 "memory_operand" "+ZC,ZC")
110 (unspec_volatile:GPR
111 [(plus:GPR (match_dup 0)
112 (match_operand:GPR 1 "arith_operand" "I,d"))]
363 [(set (match_operand:GPR 0 "memory_operand" "+ZC")
364 (unspec_volatile:GPR
[all …]
Dmips.md793 ;; This mode iterator allows 32-bit and 64-bit GPR patterns to be generated
795 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
797 ;; A copy of GPR that can be used when a pattern has two independent
879 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
902 ;; Mode attributes for GPR loads.
1217 [(match_operand:GPR 1 "reg_or_0_operand")
1218 (match_operand:GPR 2 "arith_operand")])
1227 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
1228 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
1229 (match_operand:GPR 2 "reg_or_0_operand" "dJ")])
[all …]
Dmips-dsp.md1093 (define_insn "mips_l<SHORT:size><u>x_ext<GPR:mode>_<P:mode>"
1094 [(set (match_operand:GPR 0 "register_operand" "=d")
1095 (any_extend:GPR
1101 (set_attr "mode" "<GPR:MODE>")])
1116 [(match_operand:GPR 0 "register_operand")
1127 (define_insn "mips_l<GPR:size>x_<P:mode>"
1128 [(set (match_operand:GPR 0 "register_operand" "=d")
1129 (mem:GPR (plus:P (match_operand:P 1 "register_operand" "d")
1131 "ISA_HAS_L<GPR:SIZE>X"
1132 "l<GPR:size>x\t%0,%2(%1)"
[all …]
/netbsd/src/external/gpl3/gdb/dist/sim/d10v/
Dsimops.c86 SET_HELD_SP (PSW_SM, GPR (SP_IDX)); in move_to_cr()
405 (uint16_t) GPR (OP[i])); in trace_input_func()
413 tmp = (long)((((uint32_t) GPR (OP[i])) << 16) | ((uint32_t) GPR (OP[i] + 1))); in trace_input_func()
469 (uint16_t)GPR (OP[i + 1])); in trace_input_func()
475 (uint16_t) GPR (0)); in trace_input_func()
480 (uint16_t) GPR (1)); in trace_input_func()
485 (uint16_t) GPR (2)); in trace_input_func()
593 tmp = GPR(OP[0]); in OP_4607()
643 uint16_t a = GPR (OP[0]); in OP_200()
644 uint16_t b = GPR (OP[1]); in OP_200()
[all …]
/netbsd/src/external/gpl3/gdb/dist/sim/cr16/
Dsimops.c403 (uint16_t) GPR (OP[i])); in trace_input_func()
407 tmp = (long)((((uint32_t) GPR (OP[i])) << 16) | ((uint32_t) GPR (OP[i] + 1))); in trace_input_func()
435 (uint16_t)GPR (OP[i + 1])); in trace_input_func()
544 uint16_t b = (GPR (OP[1])) & 0xff; in OP_2C_8()
547 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); in OP_2C_8()
556 uint8_t a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff; in OP_2CB_C()
559 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); in OP_2CB_C()
567 uint8_t a = (GPR (OP[0])) & 0xff; in OP_2D_8()
568 uint8_t b = (GPR (OP[1])) & 0xff; in OP_2D_8()
571 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); in OP_2D_8()
[all …]
/netbsd/src/external/gpl3/gcc/dist/gcc/config/s390/
Ds390.md674 ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated
676 (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI])
793 ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode
823 ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode
827 ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode
840 ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode
844 ;; In GPR templates, a string like sll<gk> will expand to sllg for DI
991 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T")
992 (match_operand:GPR 1 "const0_operand" "")))
993 (set (match_operand:GPR 2 "register_operand" "=d,d")
[all …]
/netbsd/src/bin/ed/
Dsub.c56 *flagp = GPR; in extract_subst_tail()
61 *flagp = GPR; in extract_subst_tail()
167 } else if ((gflag & (GPR | GLS | GNP)) && in search_and_replace()
/netbsd/src/sys/arch/sparc/sparc/
Demul.c50 #define GPR(tf, i) ((int32_t *) &tf->tf_global)[i] macro
73 *(int32_t *) val = GPR(tf, i); in readgpreg()
89 GPR(tf, i) = *(const int32_t *) val; in writegpreg()
/netbsd/src/sys/arch/evbarm/stand/boot2440/
Ddm9000.c89 #define GPR 0x1f /* gpio control */ macro
204 CSR_WRITE_1(l, GPR, GPR_PHYPWROFF); in dm9k_init()
217 CSR_WRITE_1(l, GPR, 0); in dm9k_init()
/netbsd/src/sys/arch/sparc64/sparc64/
Demul.c51 #define GPR(tf, i) ((int32_t *)(u_long)&tf->tf_global)[i] macro
74 *(int32_t *) val = GPR(tf, i); in readgpreg()
90 GPR(tf, i) = *(const int32_t *) val; in writegpreg()

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