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Searched refs:HREAD4 (Results 1 – 5 of 5) sorted by relevance

/netbsd/src/sys/arch/arm/xscale/
Dpxa2x0_ohci.c53 #define HREAD4(sc,r) bus_space_read_4((sc)->sc.iot, (sc)->sc.ioh, (r)) macro
246 hr = HREAD4(sc, USBHC_HR); in pxaohci_enable()
251 hr = HREAD4(sc, USBHC_HR); in pxaohci_enable()
255 hr = HREAD4(sc, USBHC_HR); in pxaohci_enable()
258 while (HREAD4(sc, USBHC_HR) & USBHC_HR_FSBIR) in pxaohci_enable()
262 hr = HREAD4(sc, USBHC_HR); in pxaohci_enable()
264 hr = HREAD4(sc, USBHC_HR); in pxaohci_enable()
269 hr = HREAD4(sc, USBHC_UHCRHDA); in pxaohci_enable()
278 hr = HREAD4(sc, USBHC_HR); in pxaohci_disable()
283 hr = HREAD4(sc, USBHC_HR); in pxaohci_disable()
/netbsd/src/sys/dev/acpi/
Dqcomiic.c49 #define HREAD4(sc, reg) \ macro
152 stat = HREAD4(sc, GENI_M_IRQ_STATUS); in qciic_wait()
173 stat = HREAD4(sc, GENI_RX_FIFO_STATUS); in qciic_read()
180 word = HREAD4(sc, GENI_RX_FIFO); in qciic_read()
199 stat = HREAD4(sc, GENI_TX_FIFO_STATUS); in qciic_write()
229 stat = HREAD4(sc, GENI_M_IRQ_STATUS); in qciic_exec()
251 stat = HREAD4(sc, GENI_M_IRQ_STATUS); in qciic_exec()
265 stat = HREAD4(sc, GENI_M_IRQ_STATUS); in qciic_exec()
Dqcomspmi.c102 #define HREAD4(sc, obj, reg) \ macro
217 val = HREAD4(sc, QCSPMI_REG_CORE, SPMI_VERSION); in qcspmi_attach()
244 val = HREAD4(sc, QCSPMI_REG_CORE, SPMI_ARB_APID_MAP(sc, i)); in qcspmi_attach()
250 val = HREAD4(sc, QCSPMI_REG_CNFG, SPMI_OWNERSHIP_TABLE(sc, i)); in qcspmi_attach()
300 reg = HREAD4(sc, QCSPMI_REG_OBSRVR, in qcspmi_cmd_read()
323 reg = HREAD4(sc, QCSPMI_REG_OBSRVR, in qcspmi_cmd_read()
330 reg = HREAD4(sc, QCSPMI_REG_OBSRVR, in qcspmi_cmd_read()
385 reg = HREAD4(sc, QCSPMI_REG_CHNLS, SPMI_CHAN_OFF(sc, apid) + in qcspmi_cmd_write()
Dqcomipcc.c37 #define HREAD4(sc, reg) \ macro
157 while ((reg = HREAD4(sc, IPCC_RECV_ID)) != ~0) { in qcipcc_intr()
/netbsd/src/sys/dev/sdmmc/
Dsdhc.c128 #define HREAD4(hp, reg) \ macro
178 do if ((bits) != 0) HWRITE4((hp), (reg), HREAD4((hp), (reg)) & ~(bits)); while (0)
184 do if ((bits) != 0) HWRITE4((hp), (reg), HREAD4((hp), (reg)) | (bits)); while (0)
308 sdhcver = HREAD4(hp, SDHC_ESDHC_HOST_CTL_VERSION); in sdhc_host_found()
378 caps = HREAD4(hp, SDHC_CAPABILITIES); in sdhc_host_found()
386 caps = sc->sc_caps = HREAD4(hp, SDHC_CAPABILITIES); in sdhc_host_found()
388 caps2 = sc->sc_caps2 = HREAD4(hp, SDHC_CAPABILITIES2); in sdhc_host_found()
726 uint32_t v = HREAD4(hp, i); in sdhc_suspend()
897 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED); in sdhc_card_detect()
914 r = ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_WRITE_PROTECT_SWITCH); in sdhc_write_protect()
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