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Searched refs:IMM24 (Results 1 – 9 of 9) sorted by relevance

/netbsd/src/external/gpl3/gdb/dist/opcodes/
Dm10200-opc.c84 #define IMM24 (IMM16_MEM+1) macro
88 #define IMM24_PCREL (IMM24+1)
177 { "mov", 0xf4800000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
184 { "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}},
191 { "mov", 0xf4000000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
198 { "mov", 0xf4100000, 0xfff00000, FMT_7, {AM0, MEM2(IMM24,AN1)}},
203 { "mov", 0xf4700000, 0xfffc0000, FMT_7, {IMM24, DN0}},
205 { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
209 { "movx", 0xf4b00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
212 { "movx", 0xf4300000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
[all …]
Dm10300-opc.c300 #define IMM24 (SD24+1) macro
305 #define SIMM24 (IMM24+1)
525 { "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
527 { "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
531 { "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
532 { "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
568 { "mov", 0xfdf80000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, XRN02}},
578 { "movu", 0xfd180000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
597 { "macu", 0xfd1b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
607 { "macbu", 0xfd3b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
[all …]
/netbsd/src/external/gpl3/binutils/dist/opcodes/
Dm10200-opc.c84 #define IMM24 (IMM16_MEM+1) macro
88 #define IMM24_PCREL (IMM24+1)
177 { "mov", 0xf4800000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
184 { "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}},
191 { "mov", 0xf4000000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
198 { "mov", 0xf4100000, 0xfff00000, FMT_7, {AM0, MEM2(IMM24,AN1)}},
203 { "mov", 0xf4700000, 0xfffc0000, FMT_7, {IMM24, DN0}},
205 { "mov", 0xf4740000, 0xfffc0000, FMT_7, {IMM24, AN0}},
209 { "movx", 0xf4b00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), DM0}},
212 { "movx", 0xf4300000, 0xfff00000, FMT_7, {DM0, MEM2(IMM24, AN1)}},
[all …]
Dm10300-opc.c300 #define IMM24 (SD24+1) macro
305 #define SIMM24 (IMM24+1)
525 { "mov", 0xfd8a0000, 0xffff0f00, 0, FMT_D8, AM33, {MEM2(IMM24, SP), RN2}},
527 { "mov", 0xfd9a0000, 0xffff0f00, 0, FMT_D8, AM33, {RM2, MEM2(IMM24, SP)}},
531 { "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
532 { "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
568 { "mov", 0xfdf80000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, XRN02}},
578 { "movu", 0xfd180000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
597 { "macu", 0xfd1b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
607 { "macbu", 0xfd3b0000, 0xffff0000, 0, FMT_D8, AM33, {IMM24, RN02}},
[all …]
/netbsd/src/external/gpl3/gdb/dist/sim/mn10300/
Dam33.igen3488 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
3507 // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
3526 // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
3545 // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
3569 // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
3589 // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
3608 // 1111 1101 1010 1001 Rn Rn IMM24; mul imm24,Rn
3631 // 1111 1101 1011 1001 Rn Rn IMM24; mulu imm24,Rn
3654 // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
3667 // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
[all …]
Dam33-2.igen55 // 1111 1101 1010 0111 Rm.. 0000 IMM24; dcpf (d24,Rm)
/netbsd/src/external/gpl3/gdb/dist/sim/m32c/
Dm32c.opc1133 /** 1101 0101 0010 1dst LDC #IMM24,dest */
1139 /** 1101 0101 0110 1dst LDC #IMM24,dest */
/netbsd/src/external/gpl3/gdb/dist/include/opcode/
Dh8300.h279 #define IMM24LIST IMM24, DATA5
/netbsd/src/external/gpl3/binutils/dist/include/opcode/
Dh8300.h279 #define IMM24LIST IMM24, DATA5