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Searched refs:MIPS_PHYS_TO_KSEG1 (Results 1 – 25 of 150) sorted by relevance

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/netbsd/src/sys/arch/playstation2/ee/
Ddmacreg.h41 #define DMAC_REGBASE MIPS_PHYS_TO_KSEG1(0x10008000)
47 #define D_CTRL_REG MIPS_PHYS_TO_KSEG1(0x1000e000) /* DMA control */
48 #define D_STAT_REG MIPS_PHYS_TO_KSEG1(0x1000e010) /* interrupt status */
49 #define D_PCR_REG MIPS_PHYS_TO_KSEG1(0x1000e020) /* priority control */
50 #define D_SQWC_REG MIPS_PHYS_TO_KSEG1(0x1000e030) /* interleave size */
51 #define D_RBOR_REG MIPS_PHYS_TO_KSEG1(0x1000e040) /* ring buffer addr */
52 #define D_RBSR_REG MIPS_PHYS_TO_KSEG1(0x1000e050) /* ring buffer size */
53 #define D_STADR_REG MIPS_PHYS_TO_KSEG1(0x1000e060) /* stall address */
54 #define D_ENABLER_REG MIPS_PHYS_TO_KSEG1(0x1000f520) /* DMA enable (r) */
55 #define D_ENABLEW_REG MIPS_PHYS_TO_KSEG1(0x1000f590) /* DMA enable (w) */
[all …]
Dgsreg.h32 #define GS_S_PMODE_REG MIPS_PHYS_TO_KSEG1(0x12000000)
33 #define GS_S_SMODE1_REG MIPS_PHYS_TO_KSEG1(0x12000010)
34 #define GS_S_SMODE2_REG MIPS_PHYS_TO_KSEG1(0x12000020)
35 #define GS_S_SRFSH_REG MIPS_PHYS_TO_KSEG1(0x12000030)
36 #define GS_S_SYNCH1_REG MIPS_PHYS_TO_KSEG1(0x12000040)
37 #define GS_S_SYNCH2_REG MIPS_PHYS_TO_KSEG1(0x12000050)
38 #define GS_S_SYNCV_REG MIPS_PHYS_TO_KSEG1(0x12000060)
39 #define GS_S_DISPFB1_REG MIPS_PHYS_TO_KSEG1(0x12000070)
40 #define GS_S_DISPLAY1_REG MIPS_PHYS_TO_KSEG1(0x12000080)
41 #define GS_S_DISPFB2_REG MIPS_PHYS_TO_KSEG1(0x12000090)
[all …]
Dtimerreg.h47 #define T_COUNT_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + TIMER_OFS * (x)))
48 #define T_MODE_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + \
50 #define T_COMP_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + \
58 #define T0_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10000000)
59 #define T0_MODE_REG MIPS_PHYS_TO_KSEG1(0x10000010)
60 #define T0_COMP_REG MIPS_PHYS_TO_KSEG1(0x10000020)
61 #define T0_HOLD_REG MIPS_PHYS_TO_KSEG1(0x10000030)
62 #define T1_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10000800)
63 #define T1_MODE_REG MIPS_PHYS_TO_KSEG1(0x10000810)
64 #define T1_COMP_REG MIPS_PHYS_TO_KSEG1(0x10000820)
[all …]
/netbsd/src/sys/arch/sgimips/sgimips/
Darcemu.h65 (MIPS_PHYS_TO_KSEG1((_x)) >= 0xa0000000 && \
66 MIPS_PHYS_TO_KSEG1((_x)) < 0xa0800000)
89 *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) |= 0x10; in ip6_set_pre()
91 *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) &= ~0x10; in ip6_set_pre()
99 *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) |= 0x20; in ip6_set_cs()
101 *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) &= ~0x20; in ip6_set_cs()
109 *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) |= 0x40; in ip6_set_sk()
111 *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) &= ~0x40; in ip6_set_sk()
119 if (*(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f800001) & 0x01) in ip6_get_do()
128 *(volatile uint16_t *)MIPS_PHYS_TO_KSEG1(0x1f880002) |= 0x0100; in ip6_set_di()
[all …]
Darcemu.c143 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(0x1faa0000) = 0xdeadbeef; in arcemu_identify()
145 if (*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(0x1faa0000) == 0xdeadbeef) in arcemu_identify()
149 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(0x1faa0000) = 0; in arcemu_identify()
150 (void)*(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(0x1faa0000); in arcemu_identify()
175 static void (*sgi_prom_reset)(void) = (void *)MIPS_PHYS_TO_KSEG1(0x1fc00000);
176 static void (*sgi_prom_reinit)(void) =(void *)MIPS_PHYS_TO_KSEG1(0x1fc00018);
178 (void *)MIPS_PHYS_TO_KSEG1(0x1fc00080);
503 memcfg = *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f800000) & 0x1f; in arcemu_ip6_GetMemoryDescriptor()
515 tp1 = (volatile uint8_t *)MIPS_PHYS_TO_KSEG1((pages - 4096) << 12); in arcemu_ip6_GetMemoryDescriptor()
592 MIPS_PHYS_TO_KSEG1(PIC_MEMCFG0_PHYSADDR) >> 16; in arcemu_ip12_GetMemoryDescriptor()
[all …]
/netbsd/src/sys/arch/playstation2/dev/
Dif_smapreg.h51 #define SMAP_TXFIFO_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14001000)
52 #define SMAP_TXFIFO_PTR_REG16 MIPS_PHYS_TO_KSEG1(0x14001004)
53 #define SMAP_TXFIFO_FRAME_REG8 MIPS_PHYS_TO_KSEG1(0x1400100c)
54 #define SMAP_TXFIFO_FRAME_INC_REG8 MIPS_PHYS_TO_KSEG1(0x14001010)
55 #define SMAP_TXFIFO_DATA_REG MIPS_PHYS_TO_KSEG1(0x14001100)
56 #define SMAP_RXFIFO_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14001030)
57 #define SMAP_RXFIFO_PTR_REG16 MIPS_PHYS_TO_KSEG1(0x14001034)
58 #define SMAP_RXFIFO_FRAME_REG8 MIPS_PHYS_TO_KSEG1(0x1400103c)
59 #define SMAP_RXFIFO_FRAME_DEC_REG8 MIPS_PHYS_TO_KSEG1(0x14001040)
60 #define SMAP_RXFIFO_DATA_REG MIPS_PHYS_TO_KSEG1(0x14001200)
[all …]
Dsbusreg.h32 #define SBUS_SMFLG_REG MIPS_PHYS_TO_KSEG1(0x1000f230)
36 #define SBUS_AIF_INTSR_REG16 MIPS_PHYS_TO_KSEG1(0x18000004)
37 #define SBUS_AIF_INTEN_REG16 MIPS_PHYS_TO_KSEG1(0x18000006)
39 #define SBUS_PCMCIA_EXC1_REG16 MIPS_PHYS_TO_KSEG1(0x1f801476)
40 #define SBUS_PCMCIA_CSC1_REG16 MIPS_PHYS_TO_KSEG1(0x1f801464)
41 #define SBUS_PCMCIA_IMR1_REG16 MIPS_PHYS_TO_KSEG1(0x1f801468)
42 #define SBUS_PCMCIA_TIMR_REG16 MIPS_PHYS_TO_KSEG1(0x1f80147e)
43 #define SBUS_PCMCIA3_TIMR_REG16 MIPS_PHYS_TO_KSEG1(0x1f801466)
Dspdreg.h37 #define SPD_INTR_ENABLE_REG16 MIPS_PHYS_TO_KSEG1(0x1400002a)
38 #define SPD_INTR_STATUS_REG16 MIPS_PHYS_TO_KSEG1(0x14000028)
39 #define SPD_INTR_CLEAR_REG16 MIPS_PHYS_TO_KSEG1(0x14000128)
48 #define SPD_IO_DIR_REG8 MIPS_PHYS_TO_KSEG1(0x1400002c)
49 #define SPD_IO_DATA_REG8 MIPS_PHYS_TO_KSEG1(0x1400002e)
59 #define SPD_XFR_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14000032)
60 #define SPD_HDD_IO_BASE MIPS_PHYS_TO_KSEG1(0x14000040)
61 #define SPD_IF_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14000064)
/netbsd/src/sys/arch/pmax/pmax/
Ddec_3max.c141 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0; in dec_3max_init()
147 mc_cpuspeed(MIPS_PHYS_TO_KSEG1(KN02_SYS_CLOCK), MIPS_INT_MASK_1); in dec_3max_init()
153 csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR); in dec_3max_init()
155 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr; in dec_3max_init()
172 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0; in dec_3max_bus_reset()
175 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CHKSYN) = 0; in dec_3max_bus_reset()
239 csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) & in dec_3max_intr_establish()
242 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr; in dec_3max_intr_establish()
262 csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR); in dec_3max_intr()
272 "r"(MIPS_PHYS_TO_KSEG1(KN02_SYS_CLOCK))); in dec_3max_intr()
[all …]
Ddec_5100.c100 mc_cpuspeed(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK), MIPS_INT_MASK_2); in dec_5100_init()
114 icsr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR); in dec_5100_bus_reset()
116 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR) = icsr; in dec_5100_bus_reset()
168 icsr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR); in dec_5100_intr()
175 "r"(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK))); in dec_5100_intr()
214 icsr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR); in dec_5100_memintr()
216 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR) = icsr; in dec_5100_memintr()
Ddec_3maxplus.c152 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0; in dec_3maxplus_init()
155 ioasic_base = MIPS_PHYS_TO_KSEG1(KN03_SYS_ASIC); in dec_3maxplus_init()
179 prodtype = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_REG_INTR); in dec_3maxplus_init()
201 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0; in dec_3maxplus_bus_reset()
405 erradr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR); in dec_3maxplus_errintr()
406 errsyn = MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRSYN); in dec_3maxplus_errintr()
407 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_ERRADR) = 0; in dec_3maxplus_errintr()
409 csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN03_SYS_CSR); in dec_3maxplus_errintr()
Dmemc_3min.c70 siz = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR); in kn02ba_errintr()
71 mer = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MER); in kn02ba_errintr()
72 adr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_AER); in kn02ba_errintr()
75 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; in kn02ba_errintr()
Ddec_3100.c138 mc_cpuspeed(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK), MIPS_INT_MASK_3); in dec_3100_init()
205 "r"(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK))); in dec_3100_intr()
241 csr = *(volatile uint16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR); in dec_3100_errintr()
245 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_ERRADR)); in dec_3100_errintr()
249 *(volatile uint16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR) = csr; in dec_3100_errintr()
Ddec_3min.c148 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; in dec_3min_init()
151 ioasic_base = MIPS_PHYS_TO_KSEG1(KMIN_SYS_ASIC); in dec_3min_init()
181 if ((KMIN_MSR_SIZE_16Mb & *(int *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR)) in dec_3min_init()
184 physmem_boardmax = MIPS_PHYS_TO_KSEG1(physmem_boardmax); in dec_3min_init()
200 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0; in dec_3min_bus_reset()
447 "i"(MIPS_PHYS_TO_KSEG1(KMIN_REG_IMSK))); in kn02ba_wbflush()
Ddec_maxine.c147 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT) = 0; in dec_maxine_init()
150 ioasic_base = MIPS_PHYS_TO_KSEG1(XINE_SYS_ASIC); in dec_maxine_init()
186 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_TIMEOUT) = 0; in dec_maxine_bus_reset()
371 "i"(MIPS_PHYS_TO_KSEG1(XINE_REG_IMSK))); in kn02ca_wbflush()
378 return *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(XINE_REG_FCTR); in dec_maxine_get_timecount()
/netbsd/src/sys/arch/mips/sibyte/dev/
Dsbbuswatch.c51 (void)READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_BUS_ERR_STATUS)); in sibyte_bus_watch_init()
52 WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0); in sibyte_bus_watch_init()
53 WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0); in sibyte_bus_watch_init()
76 MIPS_PHYS_TO_KSEG1(A_SCD_BUS_ERR_STATUS)); in sibyte_bus_watch_check()
82 MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS)); in sibyte_bus_watch_check()
84 WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0); in sibyte_bus_watch_check()
87 MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS)); in sibyte_bus_watch_check()
89 WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0); in sibyte_bus_watch_check()
/netbsd/src/sys/arch/hpcmips/stand/lcboot/
Dextern.h84 (__REG_1(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))) \
87 (__REG_2(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))) \
90 (__REG_4(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))) \
94 (__REG_1(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))))
96 (__REG_2(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))))
98 (__REG_4(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))))
/netbsd/src/sys/arch/evbmips/malta/
Dleds.c50 uint8_t *ledbar = (uint8_t *)MIPS_PHYS_TO_KSEG1(MALTA_LEDBAR); in led_bar()
58 uint32_t *ledbar = (uint32_t *)MIPS_PHYS_TO_KSEG1(MALTA_ASCIIWORD); in led_display_word()
66 uint8_t *leds = (uint8_t *)MIPS_PHYS_TO_KSEG1(MALTA_ASCII_BASE); in led_display_str()
79 uint8_t *leds = (uint8_t *)MIPS_PHYS_TO_KSEG1(MALTA_ASCII_BASE); in led_display_char()
/netbsd/src/sys/arch/mips/atheros/
Dar5312_board.c94 ptr = (const uint8_t *) MIPS_PHYS_TO_KSEG1(AR5312_FLASH_END - 0x1000); in ar5312_get_board_info()
124 MIPS_PHYS_TO_KSEG1(AR5312_FLASH_END-0x1000); in ar5312_get_radio_info()
132 if (end == (uint8_t *) MIPS_PHYS_TO_KSEG1(AR5312_FLASH_END)) { in ar5312_get_radio_info()
136 MIPS_PHYS_TO_KSEG1(AR5312_FLASH_END-0x1000 + 0xf8); in ar5312_get_radio_info()
Dar_console.c84 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1(platformsw->apsw_uart0_base); in earlycons_putc()
96 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1(platformsw->apsw_uart0_base); in earlycons_getc()
108 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1(platformsw->apsw_uart0_base); in earlycons_flush()
/netbsd/src/sys/arch/sgimips/hpc/
Dhpc.c385 if (!platform.badaddr((void*)MIPS_PHYS_TO_KSEG1(ga->ga_addr), in hpc_match()
436 *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr+HPC1_BIGENDIAN) = 0; in hpc_attach()
465 (void *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_2), 4)) in hpc_attach()
512 MIPS_PHYS_TO_KSEG1(sc->sc_base), ha.hpc_eeprom, in hpc_attach()
591 if (!platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + in hpc_revision()
593 reg = *(uint32_t *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + in hpc_revision()
624 if (platform.badaddr((void *)MIPS_PHYS_TO_KSEG1(ga->ga_addr + in hpc_revision()
669 value = *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + in hpc_blink()
672 *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(HPC_BASE_ADDRESS_0 + in hpc_blink()
/netbsd/src/sys/arch/pmax/ibus/
Dpm.c207 mem = (void *)MIPS_PHYS_TO_KSEG1(KN01_PHYS_FBUF_START); in pm_check_vfb()
268 kn01csr = *(volatile uint16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR); in pm_common_init()
269 pcc = (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_PCC); in pm_common_init()
270 vdac = (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_VDAC); in pm_common_init()
280 ri->ri_bits = (void *)MIPS_PHYS_TO_KSEG1(KN01_PHYS_FBUF_START); in pm_common_init()
327 *(uint8_t *)MIPS_PHYS_TO_KSEG1(KN01_PHYS_COLMASK_START) = 0xff; in pm_common_init()
386 pcc = (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_PCC); in pm_cursor_off()
397 pcc = (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_PCC); in pm_cursor_on()
415 pcc = (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_PCC); in pm_ioctl()
416 vdac = (void *)MIPS_PHYS_TO_KSEG1(KN01_SYS_VDAC); in pm_ioctl()
[all …]
/netbsd/src/sys/arch/algor/algor/
Dled.c58 #define LEDBASE MIPS_PHYS_TO_KSEG1(P4032_LED)
61 #define LEDBASE MIPS_PHYS_TO_KSEG1(P5064_LED1)
67 #define LEDBASE MIPS_PHYS_TO_KSEG1(P6032_HDSP2532_BASE + HD2532_CRAM)
/netbsd/src/sys/arch/evbmips/alchemy/
Ddbau1500.c48 (*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)))
50 (*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)) = (v))
90 whoami = *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(DBAU1500_WHOAMI)); in dbau1500_init()
/netbsd/src/sys/arch/mips/mips/
Dcache_r5k.c255 (void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0); in r4600v2_pdcache_wbinv_range_32()
259 (void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0); in r4600v2_pdcache_wbinv_range_32()
329 (void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0); in r4600v2_pdcache_inv_range_32()
334 (void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0); in r4600v2_pdcache_inv_range_32()
385 (void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0); in r4600v2_pdcache_wb_range_32()
390 (void) *(volatile int *)MIPS_PHYS_TO_KSEG1(0); in r4600v2_pdcache_wb_range_32()

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