1 /* $NetBSD: qcomgpio.c,v 1.8 2024/12/17 22:05:21 riastradh Exp $ */
2
3 /*-
4 * Copyright (c) 2024 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jared McNeill <jmcneill@invisible.ca>.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: qcomgpio.c,v 1.8 2024/12/17 22:05:21 riastradh Exp $");
34
35 #include <sys/param.h>
36 #include <sys/types.h>
37
38 #include <sys/bus.h>
39 #include <sys/cpu.h>
40 #include <sys/device.h>
41 #include <sys/evcnt.h>
42 #include <sys/gpio.h>
43 #include <sys/kmem.h>
44 #include <sys/mutex.h>
45 #include <sys/queue.h>
46
47 #include <dev/acpi/acpi_event.h>
48 #include <dev/acpi/acpi_gpio.h>
49 #include <dev/acpi/acpi_intr.h>
50 #include <dev/acpi/acpireg.h>
51 #include <dev/acpi/acpivar.h>
52 #include <dev/acpi/qcomgpioreg.h>
53
54 #include <dev/gpio/gpiovar.h>
55
56 typedef enum {
57 QCOMGPIO_X1E,
58 } qcomgpio_type;
59
60 struct qcomgpio_reserved {
61 int start;
62 int count;
63 };
64
65 struct qcomgpio_config {
66 struct qcomgpio_reserved *reserved;
67 u_int num_reserved;
68 u_int *pdc_filter;
69 u_int num_pdc_filter;
70 };
71
72 struct qcomgpio_intr_handler {
73 int (*ih_func)(void *);
74 void *ih_arg;
75 int ih_pin;
76 int ih_type;
77 struct evcnt ih_evcnt;
78 char ih_name[16];
79 LIST_ENTRY(qcomgpio_intr_handler) ih_list;
80 };
81
82 struct qcomgpio_pdcmap {
83 int pm_pin;
84 u_int pm_irq;
85 };
86
87 struct qcomgpio_softc {
88 device_t sc_dev;
89 device_t sc_gpiodev;
90 bus_space_handle_t sc_bsh;
91 bus_space_tag_t sc_bst;
92 const struct qcomgpio_config *sc_config;
93 struct gpio_chipset_tag sc_gc;
94 gpio_pin_t *sc_pins;
95 u_int sc_npins;
96 LIST_HEAD(, qcomgpio_intr_handler) sc_intrs;
97 kmutex_t sc_lock;
98
99 struct qcomgpio_pdcmap *sc_pdcmap;
100 u_int sc_npdcmap;
101 };
102
103 #define RD4(sc, reg) \
104 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
105 #define WR4(sc, reg, val) \
106 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
107
108 static int qcomgpio_match(device_t, cfdata_t, void *);
109 static void qcomgpio_attach(device_t, device_t, void *);
110
111 static bool qcomgpio_pin_reserved(struct qcomgpio_softc *, int);
112 static int qcomgpio_pin_read(void *, int);
113 static void qcomgpio_pin_write(void *, int, int);
114 static void qcomgpio_pin_ctl(void *, int, int);
115 static void * qcomgpio_intr_establish(void *, int, int, int,
116 int (*)(void *), void *);
117 static void qcomgpio_intr_disestablish(void *, void *);
118 static bool qcomgpio_intr_str(void *, int, int, char *, size_t);
119 static void qcomgpio_intr_mask(void *, void *);
120 static void qcomgpio_intr_unmask(void *, void *);
121
122 static u_int qcomgpio_acpi_num_pins(device_t, ACPI_HANDLE);
123 static void qcomgpio_acpi_fill_pdcmap(struct qcomgpio_softc *,
124 ACPI_HANDLE);
125 static int qcomgpio_acpi_translate(void *, ACPI_RESOURCE_GPIO *, void **);
126 static void qcomgpio_register_event(void *, struct acpi_event *,
127 ACPI_RESOURCE_GPIO *);
128 static int qcomgpio_intr(void *);
129
130 CFATTACH_DECL_NEW(qcomgpio, sizeof(struct qcomgpio_softc),
131 qcomgpio_match, qcomgpio_attach, NULL, NULL);
132
133 static UINT8 qcomgpio_gpio_dsm_uuid[ACPI_UUID_LENGTH] = {
134 0xa4, 0xb2, 0xb9, 0x98, 0x63, 0x16, 0x5f, 0x4a,
135 0x82, 0xf2, 0xc6, 0xc9, 0x9a, 0x39, 0x47, 0x26
136 };
137 #define QCOMGPIO_GPIO_DSM_REV 0
138 #define QCOMGPIO_GPIO_DSM_FUNC_NUM_PINS 2
139
140 static UINT8 qcomgpio_pdc_dsm_uuid[ACPI_UUID_LENGTH] = {
141 0xd4, 0x0f, 0x1b, 0x92, 0x7c, 0x56, 0xa0, 0x43,
142 0xbb, 0x14, 0x26, 0x48, 0xf7, 0xb2, 0xa1, 0x8c
143 };
144 #define QCOMGPIO_PDC_DSM_REV 0
145 #define QCOMGPIO_PDC_DSM_FUNC_CIPR 2
146
147 static struct qcomgpio_reserved qcomgpio_x1e_reserved[] = {
148 { .start = 34, .count = 2 },
149 { .start = 44, .count = 4 },
150 { .start = 72, .count = 2 },
151 { .start = 238, .count = 1 },
152 };
153
154 static int qcomgpio_x1e_pdc_filter[] = {
155 0x140, /* Interrupt storm due to missing SMI support. */
156 };
157
158 static struct qcomgpio_config qcomgpio_x1e_config = {
159 .reserved = qcomgpio_x1e_reserved,
160 .num_reserved = __arraycount(qcomgpio_x1e_reserved),
161 .pdc_filter = qcomgpio_x1e_pdc_filter,
162 .num_pdc_filter = __arraycount(qcomgpio_x1e_pdc_filter),
163 };
164
165 static const struct device_compatible_entry compat_data[] = {
166 { .compat = "QCOM0C0C", .data = &qcomgpio_x1e_config },
167 DEVICE_COMPAT_EOL
168 };
169
170 static int
qcomgpio_match(device_t parent,cfdata_t cf,void * aux)171 qcomgpio_match(device_t parent, cfdata_t cf, void *aux)
172 {
173 struct acpi_attach_args *aa = aux;
174
175 return acpi_compatible_match(aa, compat_data);
176 }
177
178 static void
qcomgpio_attach(device_t parent,device_t self,void * aux)179 qcomgpio_attach(device_t parent, device_t self, void *aux)
180 {
181 struct qcomgpio_softc * const sc = device_private(self);
182 struct acpi_attach_args *aa = aux;
183 struct gpiobus_attach_args gba;
184 ACPI_HANDLE hdl = aa->aa_node->ad_handle;
185 struct acpi_resources res;
186 struct acpi_mem *mem;
187 struct acpi_irq *irq;
188 ACPI_STATUS rv;
189 int error, pin, n;
190 void *ih;
191
192 sc->sc_dev = self;
193 sc->sc_config = acpi_compatible_lookup(aa, compat_data)->data;
194 sc->sc_bst = aa->aa_memt;
195 KASSERT(sc->sc_config != NULL);
196 LIST_INIT(&sc->sc_intrs);
197 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
198
199 rv = acpi_resource_parse(sc->sc_dev, hdl, "_CRS",
200 &res, &acpi_resource_parse_ops_default);
201 if (ACPI_FAILURE(rv)) {
202 return;
203 }
204
205 mem = acpi_res_mem(&res, 0);
206 if (mem == NULL) {
207 aprint_error_dev(self, "couldn't find mem resource\n");
208 goto done;
209 }
210
211 irq = acpi_res_irq(&res, 0);
212 if (irq == NULL) {
213 aprint_error_dev(self, "couldn't find irq resource\n");
214 goto done;
215 }
216
217 error = bus_space_map(sc->sc_bst, mem->ar_base, mem->ar_length, 0,
218 &sc->sc_bsh);
219 if (error) {
220 aprint_error_dev(self, "couldn't map registers\n");
221 goto done;
222 }
223
224 sc->sc_npdcmap = res.ar_nirq;
225 sc->sc_pdcmap = kmem_zalloc(sizeof(*sc->sc_pdcmap) * sc->sc_npdcmap,
226 KM_SLEEP);
227 for (n = 0; n < sc->sc_npdcmap; n++) {
228 sc->sc_pdcmap[n].pm_irq = acpi_res_irq(&res, n)->ar_irq;
229 sc->sc_pdcmap[n].pm_pin = -1;
230 aprint_debug_dev(self, "IRQ resource %u -> %#x\n",
231 n, sc->sc_pdcmap[n].pm_irq);
232 }
233 qcomgpio_acpi_fill_pdcmap(sc, hdl);
234
235 sc->sc_npins = qcomgpio_acpi_num_pins(self, hdl);
236 if (sc->sc_npins == 0) {
237 aprint_error_dev(self, "couldn't determine pin count!\n");
238 goto done;
239 }
240 sc->sc_pins = kmem_zalloc(sizeof(*sc->sc_pins) * sc->sc_npins,
241 KM_SLEEP);
242 for (pin = 0; pin < sc->sc_npins; pin++) {
243 sc->sc_pins[pin].pin_caps = qcomgpio_pin_reserved(sc, pin) ?
244 0 : (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
245 sc->sc_pins[pin].pin_num = pin;
246 sc->sc_pins[pin].pin_intrcaps =
247 GPIO_INTR_POS_EDGE | GPIO_INTR_NEG_EDGE |
248 GPIO_INTR_DOUBLE_EDGE | GPIO_INTR_HIGH_LEVEL |
249 GPIO_INTR_LOW_LEVEL | GPIO_INTR_MPSAFE;
250 }
251
252 sc->sc_gc.gp_cookie = sc;
253 sc->sc_gc.gp_pin_read = qcomgpio_pin_read;
254 sc->sc_gc.gp_pin_write = qcomgpio_pin_write;
255 sc->sc_gc.gp_pin_ctl = qcomgpio_pin_ctl;
256 sc->sc_gc.gp_intr_establish = qcomgpio_intr_establish;
257 sc->sc_gc.gp_intr_disestablish = qcomgpio_intr_disestablish;
258 sc->sc_gc.gp_intr_str = qcomgpio_intr_str;
259 sc->sc_gc.gp_intr_mask = qcomgpio_intr_mask;
260 sc->sc_gc.gp_intr_unmask = qcomgpio_intr_unmask;
261
262 rv = acpi_event_create_gpio(self, hdl, qcomgpio_register_event, sc);
263 if (ACPI_FAILURE(rv)) {
264 if (rv != AE_NOT_FOUND) {
265 aprint_error_dev(self, "failed to create events: %s\n",
266 AcpiFormatException(rv));
267 }
268 goto done;
269 }
270
271 ih = acpi_intr_establish(self, (uint64_t)(uintptr_t)hdl,
272 IPL_VM, false, qcomgpio_intr, sc, device_xname(self));
273 if (ih == NULL) {
274 aprint_error_dev(self, "couldn't establish interrupt\n");
275 goto done;
276 }
277
278 memset(&gba, 0, sizeof(gba));
279 gba.gba_gc = &sc->sc_gc;
280 gba.gba_pins = sc->sc_pins;
281 gba.gba_npins = sc->sc_npins;
282 sc->sc_gpiodev = config_found(self, &gba, gpiobus_print,
283 CFARGS(.iattr = "gpiobus"));
284 if (sc->sc_gpiodev != NULL) {
285 acpi_gpio_register(aa->aa_node, self,
286 qcomgpio_acpi_translate, sc);
287 }
288
289 done:
290 acpi_resource_cleanup(&res);
291 }
292
293 static u_int
qcomgpio_acpi_num_pins(device_t dev,ACPI_HANDLE hdl)294 qcomgpio_acpi_num_pins(device_t dev, ACPI_HANDLE hdl)
295 {
296 ACPI_STATUS rv;
297 ACPI_INTEGER npins;
298
299 rv = acpi_dsm_integer(hdl, qcomgpio_gpio_dsm_uuid,
300 QCOMGPIO_GPIO_DSM_REV, QCOMGPIO_GPIO_DSM_FUNC_NUM_PINS,
301 NULL, &npins);
302 if (ACPI_FAILURE(rv)) {
303 aprint_error_dev(dev, "GPIO _DSM failed: %s\n",
304 AcpiFormatException(rv));
305 return 0;
306 }
307
308 aprint_debug_dev(dev, "GPIO pin count: %u\n", (u_int)npins);
309
310 return (u_int)npins;
311 }
312
313 static void
qcomgpio_acpi_fill_pdcmap(struct qcomgpio_softc * sc,ACPI_HANDLE hdl)314 qcomgpio_acpi_fill_pdcmap(struct qcomgpio_softc *sc,
315 ACPI_HANDLE hdl)
316 {
317 ACPI_STATUS rv;
318 ACPI_OBJECT *obj;
319 u_int n, filt;
320
321 rv = acpi_dsm_typed(hdl, qcomgpio_pdc_dsm_uuid,
322 QCOMGPIO_PDC_DSM_REV, QCOMGPIO_PDC_DSM_FUNC_CIPR,
323 NULL, ACPI_TYPE_PACKAGE, &obj);
324 if (ACPI_FAILURE(rv)) {
325 aprint_error_dev(sc->sc_dev, "PDC _DSM failed: %s\n",
326 AcpiFormatException(rv));
327 return;
328 }
329
330 for (n = 0; n < obj->Package.Count; n++) {
331 ACPI_OBJECT *map = &obj->Package.Elements[n];
332 bool filter = false;
333 u_int irq, pdc;
334 int pin;
335
336 if (map->Type != ACPI_TYPE_PACKAGE ||
337 map->Package.Count < 3 ||
338 map->Package.Elements[0].Type != ACPI_TYPE_INTEGER ||
339 map->Package.Elements[1].Type != ACPI_TYPE_INTEGER ||
340 map->Package.Elements[2].Type != ACPI_TYPE_INTEGER) {
341 continue;
342 }
343
344 irq = (u_int)map->Package.Elements[2].Integer.Value;
345 pin = (int)map->Package.Elements[1].Integer.Value;
346 for (pdc = 0; pdc < sc->sc_npdcmap; pdc++) {
347 if (sc->sc_pdcmap[pdc].pm_irq == irq) {
348 for (filt = 0;
349 filt < sc->sc_config->num_pdc_filter;
350 filt++) {
351 if (sc->sc_config->pdc_filter[filt] ==
352 pdc * 64) {
353 filter = true;
354 break;
355 }
356 }
357
358 if (!filter) {
359 sc->sc_pdcmap[pdc].pm_pin = pin;
360 }
361 break;
362 }
363 }
364
365 aprint_debug_dev(sc->sc_dev,
366 "PDC irq %#x -> pin %d%s%s\n", irq, pin,
367 filter ? " (filtered)" : "",
368 pdc == sc->sc_npdcmap ? " (unused)" : "");
369 }
370
371 ACPI_FREE(obj);
372 }
373
374 static int
qcomgpio_acpi_translate(void * priv,ACPI_RESOURCE_GPIO * gpio,void ** gpiop)375 qcomgpio_acpi_translate(void *priv, ACPI_RESOURCE_GPIO *gpio, void **gpiop)
376 {
377 struct qcomgpio_softc * const sc = priv;
378 const ACPI_INTEGER vpin = gpio->PinTable[0];
379 int pin = -1;
380
381 if (vpin < sc->sc_npins) {
382 /* Virtual pin number is 1:1 mapping with hardware. */
383 pin = vpin;
384 } else if (vpin / 64 < sc->sc_npdcmap) {
385 /* Translate the virtual pin number to a hardware pin. */
386 pin = sc->sc_pdcmap[vpin / 64].pm_pin;
387 }
388
389 aprint_debug_dev(sc->sc_dev, "translate %#lx -> %u\n", vpin, pin);
390
391 if (gpiop != NULL) {
392 if (sc->sc_gpiodev != NULL) {
393 *gpiop = device_private(sc->sc_gpiodev);
394 } else {
395 device_printf(sc->sc_dev,
396 "no gpiodev for pin %#lx -> %u\n", vpin, pin);
397 pin = -1;
398 }
399 }
400
401 return pin;
402 }
403
404 static int
qcomgpio_acpi_event(void * priv)405 qcomgpio_acpi_event(void *priv)
406 {
407 struct acpi_event * const ev = priv;
408
409 acpi_event_notify(ev);
410
411 return 1;
412 }
413
414 static void
qcomgpio_register_event(void * priv,struct acpi_event * ev,ACPI_RESOURCE_GPIO * gpio)415 qcomgpio_register_event(void *priv, struct acpi_event *ev,
416 ACPI_RESOURCE_GPIO *gpio)
417 {
418 struct qcomgpio_softc * const sc = priv;
419 int irqmode;
420 void *ih;
421
422 const int pin = qcomgpio_acpi_translate(sc, gpio, NULL);
423
424 if (pin < 0) {
425 aprint_error_dev(sc->sc_dev,
426 "ignoring event for pin %#x (out of range)\n",
427 gpio->PinTable[0]);
428 return;
429 }
430
431 if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) {
432 irqmode = gpio->Polarity == ACPI_ACTIVE_HIGH ?
433 GPIO_INTR_HIGH_LEVEL : GPIO_INTR_LOW_LEVEL;
434 } else {
435 KASSERT(gpio->Triggering == ACPI_EDGE_SENSITIVE);
436 if (gpio->Polarity == ACPI_ACTIVE_LOW) {
437 irqmode = GPIO_INTR_NEG_EDGE;
438 } else if (gpio->Polarity == ACPI_ACTIVE_HIGH) {
439 irqmode = GPIO_INTR_POS_EDGE;
440 } else {
441 KASSERT(gpio->Polarity == ACPI_ACTIVE_BOTH);
442 irqmode = GPIO_INTR_DOUBLE_EDGE;
443 }
444 }
445
446 ih = qcomgpio_intr_establish(sc, pin, IPL_VM, irqmode,
447 qcomgpio_acpi_event, ev);
448 if (ih == NULL) {
449 aprint_error_dev(sc->sc_dev,
450 "couldn't register event for pin %#x\n",
451 gpio->PinTable[0]);
452 return;
453 }
454 if (gpio->Triggering == ACPI_LEVEL_SENSITIVE) {
455 acpi_event_set_intrcookie(ev, ih);
456 }
457 }
458
459 static bool
qcomgpio_pin_reserved(struct qcomgpio_softc * sc,int pin)460 qcomgpio_pin_reserved(struct qcomgpio_softc *sc, int pin)
461 {
462 u_int n;
463
464 for (n = 0; n < sc->sc_config->num_reserved; n++) {
465 if (pin >= sc->sc_config->reserved[n].start &&
466 pin < sc->sc_config->reserved[n].start +
467 sc->sc_config->reserved[n].count) {
468 return true;
469 }
470 }
471
472 return false;
473 }
474
475 static int
qcomgpio_pin_read(void * priv,int pin)476 qcomgpio_pin_read(void *priv, int pin)
477 {
478 struct qcomgpio_softc * const sc = priv;
479 uint32_t val;
480
481 if (pin < 0 || pin >= sc->sc_npins) {
482 return 0;
483 }
484 if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_INPUT) == 0) {
485 return 0;
486 }
487
488 val = RD4(sc, TLMM_GPIO_IN_OUT(pin));
489 return (val & TLMM_GPIO_IN_OUT_GPIO_IN) != 0;
490 }
491
492 static void
qcomgpio_pin_write(void * priv,int pin,int pinval)493 qcomgpio_pin_write(void *priv, int pin, int pinval)
494 {
495 struct qcomgpio_softc * const sc = priv;
496 uint32_t val;
497
498 if (pin < 0 || pin >= sc->sc_npins) {
499 return;
500 }
501 if ((sc->sc_pins[pin].pin_caps & GPIO_PIN_OUTPUT) == 0) {
502 return;
503 }
504
505 val = RD4(sc, TLMM_GPIO_IN_OUT(pin));
506 if (pinval) {
507 val |= TLMM_GPIO_IN_OUT_GPIO_OUT;
508 } else {
509 val &= ~TLMM_GPIO_IN_OUT_GPIO_OUT;
510 }
511 WR4(sc, TLMM_GPIO_IN_OUT(pin), val);
512 }
513
514 static void
qcomgpio_pin_ctl(void * priv,int pin,int flags)515 qcomgpio_pin_ctl(void *priv, int pin, int flags)
516 {
517 /* Nothing to do here, as firmware has already configured pins. */
518 }
519
520 static void *
qcomgpio_intr_establish(void * priv,int pin,int ipl,int irqmode,int (* func)(void *),void * arg)521 qcomgpio_intr_establish(void *priv, int pin, int ipl, int irqmode,
522 int (*func)(void *), void *arg)
523 {
524 struct qcomgpio_softc * const sc = priv;
525 struct qcomgpio_intr_handler *qih, *qihp;
526 uint32_t dect, pol;
527 uint32_t val;
528
529 if (pin < 0 || pin >= sc->sc_npins) {
530 return NULL;
531 }
532 if (ipl != IPL_VM) {
533 device_printf(sc->sc_dev, "%s: only IPL_VM supported\n",
534 __func__);
535 return NULL;
536 }
537
538 qih = kmem_alloc(sizeof(*qih), KM_SLEEP);
539 qih->ih_func = func;
540 qih->ih_arg = arg;
541 qih->ih_pin = pin;
542 qih->ih_type = (irqmode & GPIO_INTR_LEVEL_MASK) != 0 ?
543 IST_LEVEL : IST_EDGE;
544 snprintf(qih->ih_name, sizeof(qih->ih_name), "pin %d", pin);
545
546 mutex_enter(&sc->sc_lock);
547
548 LIST_FOREACH(qihp, &sc->sc_intrs, ih_list) {
549 if (qihp->ih_pin == qih->ih_pin) {
550 mutex_exit(&sc->sc_lock);
551 kmem_free(qih, sizeof(*qih));
552 device_printf(sc->sc_dev,
553 "%s: pin %d already establish\n", __func__, pin);
554 return NULL;
555 }
556 }
557
558 LIST_INSERT_HEAD(&sc->sc_intrs, qih, ih_list);
559
560 if ((irqmode & GPIO_INTR_LEVEL_MASK) != 0) {
561 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_LEVEL;
562 pol = (irqmode & GPIO_INTR_HIGH_LEVEL) != 0 ?
563 TLMM_GPIO_INTR_CFG_INTR_POL_CTL : 0;
564 } else {
565 KASSERT((irqmode & GPIO_INTR_EDGE_MASK) != 0);
566 if ((irqmode & GPIO_INTR_NEG_EDGE) != 0) {
567 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_NEG;
568 pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL;
569 } else if ((irqmode & GPIO_INTR_POS_EDGE) != 0) {
570 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_POS;
571 pol = TLMM_GPIO_INTR_CFG_INTR_POL_CTL;
572 } else {
573 KASSERT((irqmode & GPIO_INTR_DOUBLE_EDGE) != 0);
574 dect = TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_EDGE_BOTH;
575 pol = 0;
576 }
577 }
578
579 val = RD4(sc, TLMM_GPIO_INTR_CFG(pin));
580 val &= ~TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK;
581 val |= __SHIFTIN(dect, TLMM_GPIO_INTR_CFG_INTR_DECT_CTL_MASK);
582 val &= ~TLMM_GPIO_INTR_CFG_INTR_POL_CTL;
583 val |= pol;
584 val &= ~TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK;
585 val |= __SHIFTIN(TLMM_GPIO_INTR_CFG_TARGET_PROC_RPM,
586 TLMM_GPIO_INTR_CFG_TARGET_PROC_MASK);
587 val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN;
588 val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE;
589 WR4(sc, TLMM_GPIO_INTR_CFG(pin), val);
590
591 mutex_exit(&sc->sc_lock);
592
593 evcnt_attach_dynamic(&qih->ih_evcnt, EVCNT_TYPE_INTR,
594 NULL, device_xname(sc->sc_dev), qih->ih_name);
595
596 return qih;
597 }
598
599 static void
qcomgpio_intr_disestablish(void * priv,void * ih)600 qcomgpio_intr_disestablish(void *priv, void *ih)
601 {
602 struct qcomgpio_softc * const sc = priv;
603 struct qcomgpio_intr_handler *qih = ih;
604 uint32_t val;
605
606 evcnt_detach(&qih->ih_evcnt);
607
608 mutex_enter(&sc->sc_lock);
609
610 LIST_REMOVE(qih, ih_list);
611
612 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));
613 val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE;
614 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
615
616 mutex_exit(&sc->sc_lock);
617
618 kmem_free(qih, sizeof(*qih));
619 }
620
621 static bool
qcomgpio_intr_str(void * priv,int pin,int irqmode,char * buf,size_t buflen)622 qcomgpio_intr_str(void *priv, int pin, int irqmode, char *buf, size_t buflen)
623 {
624 struct qcomgpio_softc * const sc = priv;
625 int rv;
626
627 rv = snprintf(buf, buflen, "%s pin %d", device_xname(sc->sc_dev), pin);
628
629 return rv < buflen;
630 }
631
632 static void
qcomgpio_intr_mask(void * priv,void * ih)633 qcomgpio_intr_mask(void *priv, void *ih)
634 {
635 struct qcomgpio_softc * const sc = priv;
636 struct qcomgpio_intr_handler *qih = ih;
637 uint32_t val;
638
639 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));
640 if (qih->ih_type == IST_LEVEL) {
641 val &= ~TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN;
642 }
643 val &= ~TLMM_GPIO_INTR_CFG_INTR_ENABLE;
644 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
645 }
646
647 static void
qcomgpio_intr_unmask(void * priv,void * ih)648 qcomgpio_intr_unmask(void *priv, void *ih)
649 {
650 struct qcomgpio_softc * const sc = priv;
651 struct qcomgpio_intr_handler *qih = ih;
652 uint32_t val;
653
654 val = RD4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin));
655 if (qih->ih_type == IST_LEVEL) {
656 val |= TLMM_GPIO_INTR_CFG_INTR_RAW_STATUS_EN;
657 }
658 val |= TLMM_GPIO_INTR_CFG_INTR_ENABLE;
659 WR4(sc, TLMM_GPIO_INTR_CFG(qih->ih_pin), val);
660 }
661
662 static int
qcomgpio_intr(void * priv)663 qcomgpio_intr(void *priv)
664 {
665 struct qcomgpio_softc * const sc = priv;
666 struct qcomgpio_intr_handler *qih;
667 int rv = 0;
668
669 mutex_enter(&sc->sc_lock);
670
671 LIST_FOREACH(qih, &sc->sc_intrs, ih_list) {
672 const int pin = qih->ih_pin;
673 uint32_t val;
674
675 val = RD4(sc, TLMM_GPIO_INTR_STATUS(pin));
676 if ((val & TLMM_GPIO_INTR_STATUS_INTR_STATUS) != 0) {
677 qih->ih_evcnt.ev_count++;
678
679 rv |= qih->ih_func(qih->ih_arg);
680
681 val &= ~TLMM_GPIO_INTR_STATUS_INTR_STATUS;
682 WR4(sc, TLMM_GPIO_INTR_STATUS(pin), val);
683 }
684 }
685
686 mutex_exit(&sc->sc_lock);
687
688 return rv;
689 }
690