| /netbsd/src/external/gpl3/binutils/dist/opcodes/ |
| D | micromips-opc.c | 211 #define WR_1 INSN_WRITE_1 macro
217 #define MOD_1 (WR_1|RD_1)
302 {"li", "md,mI", 0xec00, 0xfc00, WR_1, …
303 {"li", "t,j", 0x30000000, 0xfc1f0000, WR_1, …
304 {"li", "t,i", 0x50000000, 0xfc1f0000, WR_1, …
307 {"move", "mp,mj", 0x0c00, 0xfc00, WR_1|RD_2, 0, …
308 {"move", "d,s", 0x00000290, 0xffe007ff, WR_1|RD_2, …
309 {"move", "d,s", 0x58000150, 0xffe007ff, WR_1|RD_2, …
310 {"move", "d,s", 0x00000150, 0xffe007ff, WR_1|RD_2, …
320 {"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D, …
[all …]
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| D | mips-opc.c | 232 #define WR_1 INSN_WRITE_1 macro
239 #define MOD_1 (WR_1|RD_1)
457 {"li", "t,j", 0x24000000, 0xffe00000, WR_1, …
458 {"li", "t,i", 0x34000000, 0xffe00000, WR_1, …
461 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_1|RD_2, …
462 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_1|RD_2, INSN2_ALI…
463 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_1|RD_2, INSN2_ALI…
470 {"lapc", "s,-A", 0xec000000, 0xfc180000, WR_1, RD_pc, …
476 {"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, …
477 {"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, …
[all …]
|
| D | mips16-opc.c | 165 #define WR_1 INSN_WRITE_1 macro
171 #define MOD_1 (WR_1|RD_1)
214 {"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC|AL,…
216 {"addiu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, …
220 {"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, …
221 {"addiu", "x,S,V", 0x0000, 0xf800, WR_1, SH|RD_SP,…
222 {"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, …
223 {"addiu", "x,S,V", 0xf0000000, 0xf800f8e0, WR_1, RD_SP, …
224 {"addiu", "x,G,V", 0xf0000020, 0xf800f8e0, WR_1|RD_2, 0, …
225 {"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, SH, …
[all …]
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| D | ChangeLog-2013 | 342 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
348 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
358 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
|
| /netbsd/src/external/gpl3/gdb/dist/opcodes/ |
| D | micromips-opc.c | 211 #define WR_1 INSN_WRITE_1 macro
217 #define MOD_1 (WR_1|RD_1)
302 {"li", "md,mI", 0xec00, 0xfc00, WR_1, …
303 {"li", "t,j", 0x30000000, 0xfc1f0000, WR_1, …
304 {"li", "t,i", 0x50000000, 0xfc1f0000, WR_1, …
307 {"move", "mp,mj", 0x0c00, 0xfc00, WR_1|RD_2, 0, …
308 {"move", "d,s", 0x00000290, 0xffe007ff, WR_1|RD_2, …
309 {"move", "d,s", 0x58000150, 0xffe007ff, WR_1|RD_2, …
310 {"move", "d,s", 0x00000150, 0xffe007ff, WR_1|RD_2, …
320 {"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D, …
[all …]
|
| D | mips-opc.c | 232 #define WR_1 INSN_WRITE_1 macro
239 #define MOD_1 (WR_1|RD_1)
457 {"li", "t,j", 0x24000000, 0xffe00000, WR_1, …
458 {"li", "t,i", 0x34000000, 0xffe00000, WR_1, …
461 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_1|RD_2, …
462 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_1|RD_2, INSN2_ALI…
463 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_1|RD_2, INSN2_ALI…
470 {"lapc", "s,-A", 0xec000000, 0xfc180000, WR_1, RD_pc, …
476 {"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, …
477 {"campv", "d,s", 0x70000035, 0xfc1f07ff, WR_1|RD_2, …
[all …]
|
| D | mips16-opc.c | 165 #define WR_1 INSN_WRITE_1 macro
171 #define MOD_1 (WR_1|RD_1)
214 {"la", "x,A", 0x0800, 0xf800, WR_1, RD_PC|AL,…
216 {"addiu", "y,x,F", 0x4000, 0xf810, WR_1|RD_2, 0, …
220 {"addiu", "x,P,V", 0x0800, 0xf800, WR_1, RD_PC, …
221 {"addiu", "x,S,V", 0x0000, 0xf800, WR_1, SH|RD_SP,…
222 {"addiu", "x,S,V", 0x0000, 0xf800, WR_1, RD_SP, …
223 {"addiu", "x,S,V", 0xf0000000, 0xf800f8e0, WR_1, RD_SP, …
224 {"addiu", "x,G,V", 0xf0000020, 0xf800f8e0, WR_1|RD_2, 0, …
225 {"addu", "z,v,y", 0xe001, 0xf803, WR_1|RD_2|RD_3, SH, …
[all …]
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| D | ChangeLog-2013 | 342 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
348 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
358 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
|