| /netbsd/src/external/gpl3/gdb/dist/gdb/testsuite/gdb.disasm/ |
| D | t10_and.s | 8 and.b #0x12:8,r1h ;e112
9 and.b #0x12:8,@er1 ;7d10e012
10 and.b #0x12:8,@(0x3:2,er1) ;01776818e012
11 and.b #0x12:8,@er1+ ;01746c18e012
12 and.b #0x12:8,@-er1 ;01776c18e012
13 and.b #0x12:8,@+er1 ;01756c18e012
14 and.b #0x12:8,@er1- ;01766c18e012
15 and.b #0x12:8,@(0x1234:16,er1) ;01746e181234e012
16 and.b #0x12:8,@(0x12345678:32,er1) ;78146a2812345678e012
17 and.b #0x12:8,@(0x1234:16,r2l.b) ;01756e281234e012
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| /netbsd/src/external/gpl3/gcc/dist/gcc/config/i386/ |
| D | btver2.md | 5 ;; GCC is free software; you can redistribute it and/or modify
22 ;; double (fast path double) and vector instructions.
23 ;; Direct instrucions are decoded and convereted into 1 cop
24 ;; Double instrucions are decoded and converetd into 2 cops
25 ;; Vector instrucions are microcoded and they generated converted to
65 ;; There are 2 AGU pipes one for load and one for store.
73 ;; MUL and DIV operations can take place in to ALU pipe1.
99 (and (eq_attr "cpu" "btver2")
107 (and (eq_attr "cpu" "btver2")
108 (and (eq_attr "memory" "load")
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| D | znver.md | 5 ;; GCC is free software; you can redistribute it and/or modify
24 ;; AMD znver1, znver2 and znver3 Scheduling
26 ;; AGU pipes and floating point execution units.
29 ;; Decoders unit has 4 decoders and all of them can decode fast path
30 ;; and vector type instructions.
55 ;; 2 AGU pipes in znver1 and 3 AGU pipes in znver2 and znver3
66 ;; Store operations differs between znver1, znver2 and znver3 because extra AGU
98 (and (eq_attr "cpu" "znver1")
103 (and (eq_attr "cpu" "znver2,znver3")
109 (and (eq_attr "cpu" "znver1")
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| D | znver4.md | 5 ;; GCC is free software; you can redistribute it and/or modify
26 ;; AGU pipes, branch, floating point execution and fp store units.
29 ;; Decoders unit has 4 decoders and all of them can decode fast path
30 ;; and vector type instructions.
88 ;; Separate fp store and fp-to-int store. Although there are 2 store pipes, the
97 (and (eq_attr "cpu" "znver4")
98 (and (eq_attr "znver1_decode" "double")
99 (and (eq_attr "type" "imov")
104 (and (eq_attr "cpu" "znver4")
105 (and (eq_attr "znver1_decode" "double")
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| D | slm.md | 6 ;; GCC is free software; you can redistribute it and/or modify
20 ;; Silvermont has 2 out-of-order IEC, 2 in-order FEC and 1 in-order MEC.
28 ;; SLM has two ports: port 0 and port 1 connecting to all execution units
40 ;; Some EUs have duplicated copied and can be accessed via either
71 ;;; issue in port 0, some in port 0 and some in either port.
76 ;;; Complex macro-instruction has variants of latency, and uses both ports.
80 (and (eq_attr "cpu" "slm")
81 (and (eq_attr "type" "other")
87 (and (eq_attr "cpu" "slm")
88 (and (eq_attr "type" "other")
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| D | glm.md | 6 ;; GCC is free software; you can redistribute it and/or modify
20 ;; Goldmont has 3 out-of-order IEC, 2 out-of--order FEC and out-of-order MEC.
28 ;; IEC has three execution ports - IEC-0, IEC-1 and IEC-2.
29 ;; FPC has two execution ports - FPC-0 and FPC-1.
30 ;; MEC has two execution ports - MEC-0 (load) and MEC-1 (store0.
34 ;; Some EUs have duplicated copied and can be accessed via either ports 0, 1 or 2.
51 ;;; fmul insn can have 4 or 5 cycles latency for scalar and vector types.
72 (and (eq_attr "cpu" "glm")
73 (and (eq_attr "type" "other")
79 (and (eq_attr "cpu" "glm")
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| D | bdver3.md | 5 ;; GCC is free software; you can redistribute it and/or modify
19 ;; AMD bdver3 and bdver4 Scheduling
21 ;; The bdver3 and bdver4 contains three pipelined FP units and two integer
22 ;; units. ;; Fetching and decoding logic is different from previous fam15
24 ;; and two decode units are available. The decode units therefore decode
30 ;; bdver3 and bdver4 belong to fam15 processors. We use the same insn
105 (and (eq_attr "cpu" "bdver3,bdver4")
110 (and (eq_attr "cpu" "bdver3,bdver4")
115 (and (eq_attr "cpu" "bdver3,bdver4")
120 (and (eq_attr "cpu" "bdver3,bdver4")
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| D | haswell.md | 1 ;; Scheduling for Haswell and derived processors.
6 ;; GCC is free software; you can redistribute it and/or modify
22 ;; two MU for load and one MU for store.
58 ;; port 7 for store address calculations, port 4 for memory stores, and
59 ;; ports 0, 1, 5 and 6 for everything else.
77 (and (eq_attr "cpu" "generic,haswell")
82 (and (eq_attr "cpu" "generic,haswell")
87 ;; imovx always decodes to one uop, and also doesn't use the integer
90 (and (eq_attr "cpu" "generic,haswell")
91 (and (eq_attr "memory" "none")
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| D | athlon.md | 5 ;; GCC is free software; you can redistribute it and/or modify
21 ;; The Athlon does contain three pipelined FP units, three integer units and
28 ;; Three DirectPath instructions decoders and only one VectorPath decoder
33 ;; it to the specialized integer (18 entry) and fp (36 entry) schedulers.
41 (and (eq_attr "type" "push")
44 (and (eq_attr "type" "fmov")
45 (and (eq_attr "memory" "load,store")
72 ;; to decode when decoder2 and decoder0 in next cycle
77 ;; and other units, we model decoder as two stage fully pipelined unit
78 ;; and only double decoded instruction may occupy unit in the first cycle.
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| D | bdver1.md | 5 ;; GCC is free software; you can redistribute it and/or modify
21 ;; The bdver1 contains four pipelined FP units, two integer units and
28 ;; Three DirectPath instructions decoders and only one VectorPath decoder
47 ;; to decode when decoder2 and decoder0 in next cycle
52 ;; and other units, we model decoder as two stage fully pipelined unit
53 ;; and only double decoded instruction may occupy unit in the first cycle.
59 ;; We solve that by specialized vector decoder unit and exclusion set.
101 ;; integer operations start to execute at stage 9 for athlon and 11 for K8
104 ;; NOTE: the above information was just copied from athlon.md, and was not
130 (and (eq_attr "cpu" "bdver1,bdver2")
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| D | core2.md | 1 ;; Scheduling for Core 2 and derived processors.
6 ;; GCC is free software; you can redistribute it and/or modify
26 ;; The major difference from the P6 pipeline is one extra decoder, and
30 ;; The core2_idiv, core2_fdiv and core2_ssediv automata are used to
31 ;; model issue latencies of idiv, fdiv and ssediv type insns.
56 ;; decoder 0, and this takes an unspecified number of cycles.
66 ;; c2_decoder1 and c2_decoder2 from being reserved until c2_decoder 0 is
77 ;; port 3 for store address calculations, port 4 for memory stores, and
78 ;; ports 0, 1 and 5 for everything else.
92 ;; reg-reg operation, 1 uop per load on port 2. and 2 uops per store
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| D | atom.md | 6 ;; GCC is free software; you can redistribute it and/or modify
31 ;; Atom has two ports: port 0 and port 1 connecting to all execution units
41 ;; Some EUs have duplicated copied and can be accessed via either
46 ;;; Complex multi-op macro-instructoins need both ports and all EUs
53 ;;; issue in port 0, some in port 0 and some in either port.
58 ;;; Some insn issues in port 0 with 3 cycle latency and 1 cycle tput
84 ;;; Complex macro-instruction has variants of latency, and uses both ports.
88 (and (eq_attr "cpu" "atom")
89 (and (eq_attr "type" "other")
95 (and (eq_attr "cpu" "atom")
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| D | ppro.md | 6 ;; GCC is free software; you can redistribute it and/or modify
21 ;; and Xeon lines of CPUs. The DFA scheduler description in this file is
38 ;; So, the P6 CPUs have out-of-order cores, but the instruction decoder and
61 ;; - Figure out where the p0 and p1 reservations come from. These
65 ;; The ppro_idiv and ppro_fdiv automata are used to model issue
66 ;; latencies of idiv and fdiv type insns.
71 ;; two uops, and simple read-modify instructions also take two uops.
80 ;; decoder 0, and this takes an unspecified number of cycles.
89 ;; decoder1 and decoder2 from being reserved until decoder 0 is
125 ;; reg-reg operation, 1 uop per load on port 2. and 2 uops per store
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| /netbsd/src/external/gpl3/gcc/dist/gcc/config/m68k/ |
| D | cf.md | 1 ;; ColdFire V1, V2, V3 and V4/V4e DFA description.
7 ;; GCC is free software; you can redistribute it and/or modify
46 (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
68 ;; subscribed and adjust number of prefetched instruction words accordingly.
132 ;; Load from a memory location and store to a memory location.
146 ;; Load from an indexed location and store to a memory location.
160 ;; Load from a memory location and store to an indexed location.
302 ;; ??? pushing and poping return address to and from the stack.
338 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
348 (and (and (and (eq_attr "cpu" "cfv1,cfv2,cfv3")
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| /netbsd/src/crypto/external/bsd/openssl/lib/libcrypto/arch/powerpc64/ |
| D | sha256-ppc.S | 133 and 5,6,12
146 and 5,8,9
147 and 0,8,10
151 and 0,9,10
162 and 5,12,11
175 and 5,15,8
176 and 0,15,9
180 and 0,8,9
191 and 5,11,10
204 and 5,14,15
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| D | sha512-ppc.S | 133 and 5,6,12
146 and 5,8,9
147 and 0,8,10
151 and 0,9,10
162 and 5,12,11
175 and 5,15,8
176 and 0,15,9
180 and 0,8,9
191 and 5,11,10
204 and 5,14,15
[all …]
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| /netbsd/src/crypto/external/bsd/openssl/lib/libcrypto/arch/powerpc/ |
| D | sha512-ppc.S | 133 and 5,6,12
146 and 5,8,9
147 and 0,8,10
151 and 0,9,10
162 and 5,12,11
175 and 5,15,8
176 and 0,15,9
180 and 0,8,9
191 and 5,11,10
204 and 5,14,15
[all …]
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| D | sha256-ppc.S | 133 and 5,6,12
146 and 5,8,9
147 and 0,8,10
151 and 0,9,10
162 and 5,12,11
175 and 5,15,8
176 and 0,15,9
180 and 0,8,9
191 and 5,11,10
204 and 5,14,15
[all …]
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| /netbsd/src/external/gpl3/gcc/dist/gcc/config/s390/ |
| D | 2097.md | 7 ; - The two pipelines are called S and T, respectively.
16 ;; Automaton and components.
25 ; Both pipelines can execute a branch instruction, and branch
32 (and (eq_attr "cpu" "z10")
37 ; Z10 operand and result forwarding.
48 ; Forwarding from z10_fwd and z10_fr to z10_super.
64 ; Forwarding from z10_super to frz10_ and z10_rec.
76 ; Forwarding from z10_fwd and z10_fr to z10_rec and z10_fr.
108 (and (and (eq_attr "cpu" "z10")
110 (and (eq_attr "atype" "reg")
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| D | 2827.md | 7 ;; GCC is free software; you can redistribute it and/or modify it under
38 (and (eq_attr "cpu" "zEC12")
42 (and (eq_attr "cpu" "zEC12")
46 (and (eq_attr "cpu" "zEC12")
50 (and (eq_attr "cpu" "zEC12")
54 (and (eq_attr "cpu" "zEC12")
58 (and (eq_attr "cpu" "zEC12")
62 (and (eq_attr "cpu" "zEC12")
66 (and (eq_attr "cpu" "zEC12")
70 (and (eq_attr "cpu" "zEC12")
[all …]
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| D | 2817.md | 8 ;; GCC is free software; you can redistribute it and/or modify it under
42 ;; Try to keep cracked and alone insns together in a clump. This will also
49 ;; latency == 0. This reduces life ranges and spilling. We want to increase
53 (and (eq_attr "cpu" "z196")
54 (and (eq_attr "type" "load,store,lr")
59 (and (eq_attr "cpu" "z196")
60 (and (eq_attr "type" "integer,la,larl,other")
61 (and (eq_attr "z196prop" "none")
66 (and (eq_attr "cpu" "z196")
67 (and (eq_attr "type" "integer,la,larl,other")
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| /netbsd/src/external/gpl3/gcc/dist/gcc/config/mips/ |
| D | i6400.md | 7 ;; GCC is free software; you can redistribute it and/or modify it
50 (and (eq_attr "cpu" "i6400")
51 (and (eq_attr "mode" "!V2DI")
57 (and (eq_attr "cpu" "i6400")
63 (and (eq_attr "cpu" "i6400")
69 (and (eq_attr "cpu" "i6400")
73 ;; and, or, xor, ilv, pck, fill, splat
75 (and (eq_attr "cpu" "i6400")
81 (and (eq_attr "cpu" "i6400")
87 (and (eq_attr "cpu" "i6400")
[all …]
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| D | 10000.md | 6 ;; GCC is free software; you can redistribute it and/or modify it
25 ;; The int queue feeds ALU1 and ALU2.
26 ;; The fp queue feeds the fp-adder and fp-multiplier.
29 ;; However, we define the fp-adder and fp-multiplier as
31 ;; divided into fp-multiplier, fp-division, and
33 ;; issue and completion logic, yet can operate in
37 ;; and it helps to reduce the size of the automata.
50 ;; R10k Loads and Stores.
52 (and (eq_attr "cpu" "r10000")
57 (and (eq_attr "cpu" "r10000")
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| D | 74k.md | 2 ;; Contributed by MIPS Technologies and CodeSourcery.
12 ;; GCC is free software; you can redistribute it and/or modify it
41 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
47 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
52 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
57 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
64 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
70 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
76 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
82 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
[all …]
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| /netbsd/src/external/gpl3/gcc/dist/gcc/config/arm/ |
| D | xgene1.md | 7 ;; GCC is free software; you can redistribute it and/or modify it
63 (and (eq_attr "tune" "xgene1")
68 (and (eq_attr "tune" "xgene1")
73 (and (eq_attr "tune" "xgene1")
78 (and (eq_attr "tune" "xgene1")
83 (and (eq_attr "tune" "xgene1")
88 (and (eq_attr "tune" "xgene1")
93 (and (eq_attr "tune" "xgene1")
98 (and (eq_attr "tune" "xgene1")
103 (and (eq_attr "tune" "xgene1")
[all …]
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