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Searched refs:h_gr (Results 1 – 23 of 23) sorted by relevance

/netbsd/src/external/gpl3/gdb/dist/sim/lm32/
Dsem-switch.c312 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); in CASE()
313 CPU (h_gr[FLD (f_r2)]) = opval; in CASE()
331 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))); in CASE()
332 CPU (h_gr[FLD (f_r1)]) = opval; in CASE()
350 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); in CASE()
351 CPU (h_gr[FLD (f_r2)]) = opval; in CASE()
369 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))); in CASE()
370 CPU (h_gr[FLD (f_r1)]) = opval; in CASE()
388 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16)); in CASE()
389 CPU (h_gr[FLD (f_r1)]) = opval; in CASE()
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Dsem.c212 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); in SEM_FN_NAME()
213 CPU (h_gr[FLD (f_r2)]) = opval; in SEM_FN_NAME()
233 SI opval = ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))); in SEM_FN_NAME()
234 CPU (h_gr[FLD (f_r1)]) = opval; in SEM_FN_NAME()
254 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)])); in SEM_FN_NAME()
255 CPU (h_gr[FLD (f_r2)]) = opval; in SEM_FN_NAME()
275 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))); in SEM_FN_NAME()
276 CPU (h_gr[FLD (f_r1)]) = opval; in SEM_FN_NAME()
296 SI opval = ANDSI (CPU (h_gr[FLD (f_r0)]), SLLSI (FLD (f_uimm), 16)); in SEM_FN_NAME()
297 CPU (h_gr[FLD (f_r1)]) = opval; in SEM_FN_NAME()
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Dcpu.c52 return CPU (h_gr[regno]); in lm32bf_h_gr_get()
60 CPU (h_gr[regno]) = newval; in lm32bf_h_gr_set()
Dcpu.h50 SI h_gr[32]; member
51 #define GET_H_GR(a1) CPU (h_gr)[a1]
52 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
/netbsd/src/external/gpl3/gdb/dist/sim/m32r/
Ddecode.c603 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32rbf_decode()
604 FLD (i_sr) = & CPU (h_gr)[f_r2]; in m32rbf_decode()
637 FLD (i_sr) = & CPU (h_gr)[f_r2]; in m32rbf_decode()
638 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32rbf_decode()
670 FLD (i_sr) = & CPU (h_gr)[f_r2]; in m32rbf_decode()
671 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32rbf_decode()
703 FLD (i_sr) = & CPU (h_gr)[f_r2]; in m32rbf_decode()
704 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32rbf_decode()
733 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32rbf_decode()
762 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32rbf_decode()
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Ddecodex.c733 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32rxf_decode()
734 FLD (i_sr) = & CPU (h_gr)[f_r2]; in m32rxf_decode()
767 FLD (i_sr) = & CPU (h_gr)[f_r2]; in m32rxf_decode()
768 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32rxf_decode()
800 FLD (i_sr) = & CPU (h_gr)[f_r2]; in m32rxf_decode()
801 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32rxf_decode()
833 FLD (i_sr) = & CPU (h_gr)[f_r2]; in m32rxf_decode()
834 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32rxf_decode()
863 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32rxf_decode()
892 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32rxf_decode()
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Ddecode2.c792 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32r2f_decode()
793 FLD (i_sr) = & CPU (h_gr)[f_r2]; in m32r2f_decode()
826 FLD (i_sr) = & CPU (h_gr)[f_r2]; in m32r2f_decode()
827 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32r2f_decode()
859 FLD (i_sr) = & CPU (h_gr)[f_r2]; in m32r2f_decode()
860 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32r2f_decode()
892 FLD (i_sr) = & CPU (h_gr)[f_r2]; in m32r2f_decode()
893 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32r2f_decode()
922 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32r2f_decode()
951 FLD (i_dr) = & CPU (h_gr)[f_r1]; in m32r2f_decode()
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Dm32r2.c66 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler()
71 return CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_get_handler()
104 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler()
105 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32r2f_h_cr_set_handler()
110 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32r2f_h_cr_set_handler()
111 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32r2f_h_cr_set_handler()
124 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler()
130 CPU (h_gr[H_GR_SP]) = newval; in m32r2f_h_cr_set_handler()
238 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; in check_load_stall() local
241 && (h_gr & (1 << regno)) != 0) in check_load_stall()
Dm32rx.c66 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler()
71 return CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_get_handler()
104 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler()
105 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rxf_h_cr_set_handler()
110 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rxf_h_cr_set_handler()
111 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rxf_h_cr_set_handler()
124 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler()
130 CPU (h_gr[H_GR_SP]) = newval; in m32rxf_h_cr_set_handler()
238 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; in check_load_stall() local
241 && (h_gr & (1 << regno)) != 0) in check_load_stall()
Dm32r.c164 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler()
169 return CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_get_handler()
202 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler()
203 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]); in m32rbf_h_cr_set_handler()
208 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]); in m32rbf_h_cr_set_handler()
209 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]); in m32rbf_h_cr_set_handler()
222 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler()
228 CPU (h_gr[H_GR_SP]) = newval; in m32rbf_h_cr_set_handler()
348 UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs; in check_load_stall() local
351 && (h_gr & (1 << regno)) != 0) in check_load_stall()
Dcpu.c52 return CPU (h_gr[regno]); in m32rbf_h_gr_get()
60 CPU (h_gr[regno]) = newval; in m32rbf_h_gr_set()
Dcpu2.c52 return CPU (h_gr[regno]); in m32r2f_h_gr_get()
60 CPU (h_gr[regno]) = newval; in m32r2f_h_gr_set()
Dcpux.c52 return CPU (h_gr[regno]); in m32rxf_h_gr_get()
60 CPU (h_gr[regno]) = newval; in m32rxf_h_gr_set()
Dcpu.h50 SI h_gr[16]; member
51 #define GET_H_GR(a1) CPU (h_gr)[a1]
52 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
119 UINT h_gr; member
Dcpux.h50 SI h_gr[16]; member
51 #define GET_H_GR(a1) CPU (h_gr)[a1]
52 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
Dcpu2.h50 SI h_gr[16]; member
51 #define GET_H_GR(a1) CPU (h_gr)[a1]
52 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
Dsem2-switch.c1031 CPU (h_gr[((UINT) 14)]) = opval; in CASE()
1059 CPU (h_gr[((UINT) 14)]) = opval; in CASE()
1088 CPU (h_gr[((UINT) 14)]) = opval; in CASE()
1121 CPU (h_gr[((UINT) 14)]) = opval; in CASE()
1271 CPU (h_gr[((UINT) 14)]) = opval; in CASE()
1304 CPU (h_gr[((UINT) 14)]) = opval; in CASE()
1779 CPU (h_gr[((UINT) 14)]) = opval; in CASE()
3822 CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14); in CASE()
3877 CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14); in CASE()
4023 CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14); in CASE()
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Dsemx-switch.c1024 CPU (h_gr[((UINT) 14)]) = opval; in CASE()
1052 CPU (h_gr[((UINT) 14)]) = opval; in CASE()
1081 CPU (h_gr[((UINT) 14)]) = opval; in CASE()
1114 CPU (h_gr[((UINT) 14)]) = opval; in CASE()
1264 CPU (h_gr[((UINT) 14)]) = opval; in CASE()
1297 CPU (h_gr[((UINT) 14)]) = opval; in CASE()
1611 CPU (h_gr[((UINT) 14)]) = opval; in CASE()
3654 CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14); in CASE()
3709 CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14); in CASE()
3855 CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_SI_14); in CASE()
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Dsem-switch.c840 CPU (h_gr[((UINT) 14)]) = opval; in CASE()
868 CPU (h_gr[((UINT) 14)]) = opval; in CASE()
1184 CPU (h_gr[((UINT) 14)]) = opval; in CASE()
Dsem.c740 CPU (h_gr[((UINT) 14)]) = opval; in SEM_FN_NAME()
770 CPU (h_gr[((UINT) 14)]) = opval; in SEM_FN_NAME()
1114 CPU (h_gr[((UINT) 14)]) = opval; in SEM_FN_NAME()
/netbsd/src/external/gpl3/gdb/dist/sim/iq2000/
Dcpu.h53 SI h_gr[32]; member
54 #define GET_H_GR(index) (((index) == (0))) ? (0) : (CPU (h_gr[index]))
61 CPU (h_gr[(index)]) = (x);\
/netbsd/src/external/gpl3/gdb/dist/sim/frv/
Dfrv.c140 return CPU (h_gr[gr]); in frvbf_h_gr_get_handler()
151 CPU (h_gr[gr]) = newval; in frvbf_h_gr_set_handler()
Dcpu.h125 USI h_gr[64]; member