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/netbsd/src/external/bsd/elftosb/dist/bdfiles/
Dbasic_test_cmd.e44 # load dcd
45 load dcd {{ 00 11 22 33 }} > 0;
47 # same load without dcd
48 load {{ 00 11 22 33 }} > 0;
56 # load a simple IVT to an absolute address
58 load ivt (entry=hello:_start) > 0x1000;
60 # load simple IVT. the IVT self address is set explicitly in the IVT declaration,
61 # giving the IVT a natural address so you don't have to tell where to load it.
62 load ivt (entry=hello:_start, self=0x1000);
64 load ivt (entry=hello:_start, self=0x1000, csf=0x2000, dcd=0);
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Dtest_cmd.e64 # load 0.w > ocram_start..ocram_end; # word fill all ocram with 0
66 # load hostlink; # load all of hostlink source
68 # load 0x1000ffff.w > 0x1000; # load a word to address 0x1000
69 # load 0x55aa.h > 0x2000; # load a half-word to address 0x2000
70 # load redboot; # load all sections of redboo…
73 # load $.*.text; # load some sections to their natural l…
79 # load $* > .; # load all sections of hostli…
81 # load $.text > 0x1000; # load .text section to address 0x1000
83 # load 0x55.b > 0x0..0x4000; # fill 0 through 0x4000 with byte pattern 0x55
86 # load $*.text from hostlink > .; # load sections match "*.text" from hostlink to d…
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Dcomplex.bd81 load dcd {{ 00 11 22 33 }} > 0;
82 load srecfile;
107 load 0x1234.h > 0..10K;
113 load halfword > 0..1K;
120 load 0xff.b > 32K..32K + sizeof(elffile:printMessage);
123 load {{ 00 01 02 03 04 }} > 1K;
125 // load all sections except .mytext
126 load ~$.mytext;
132 load "hi from section 1" > :szMsg;
139 load 0.w > (elffile:endOfLine)..(elffile:endOfLine + sizeof(elffile:endOfLine));
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/netbsd/src/tests/lib/libc/stdlib/
Dt_getopt.sh31 load: $1
57 load="c:d"
59 h_getopt "${load}" "foo -c 1 -d foo" "c=1,d|1"
60 h_getopt "${load}" "foo -d foo bar" "d|2"
61 h_getopt "${load}" "foo -c 2 foo bar" "c=2|2"
62 h_getopt "${load}" "foo -e 1 foo bar" "!?|3"
63 h_getopt "${load}" "foo -d -- -c 1" "d|2"
64 h_getopt "${load}" "foo -c- 1" "c=-|1"
65 h_getopt "${load}" "foo -d - 1" "d|2"
88 load="optstring: abc:
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/netbsd/src/external/gpl3/gcc/dist/gcc/config/i386/
Dbtver2.md65 ;; There are 2 AGU pipes one for load and one for store.
67 (define_cpu_unit "btver2-load" "btver2_agu")
80 btver2-load+btver2-store")
95 btver2-load+btver2-store")
101 "btver2-double,btver2-load")
108 (and (eq_attr "memory" "load")
110 "btver2-direct,btver2-load,btver2-alu")
119 (and (eq_attr "memory" "load")
121 "btver2-direct,btver2-load,btver2-alu")
156 (eq_attr "memory" "load,both"))))
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Dznver4.md62 ;; Load is 4 cycles. We do not model reservation of load unit.
63 (define_reservation "znver4-load" "znver4-agu-reserve")
107 (eq_attr "memory" "load"))))
108 "znver4-double,znver4-load,znver4-ieu")
120 (eq_attr "memory" "load")))
121 "znver4-direct,znver4-load,znver4-ieu")
134 "znver4-direct,znver4-load,znver4-store")
140 (eq_attr "memory" "load")))
141 "znver4-direct,znver4-load")
147 "znver4-direct,znver4-load,znver4-store")
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Dznver.md63 ;; Load is 4 cycles. We do not model reservation of load unit.
64 ;;(define_reservation "znver1-load" "znver1-agu-reserve, nothing, nothing, nothing")
65 (define_reservation "znver1-load" "znver1-agu-reserve")
123 "znver1-direct,znver1-load,znver1-store")
128 "znver1-direct,znver1-load,znver2-store")
133 (eq_attr "memory" "load")))
134 "znver1-direct,znver1-load")
140 "znver1-direct,znver1-load,znver1-store")
145 "znver1-direct,znver1-load,znver2-store")
170 "znver1-direct,znver1-load, znver1-ieu1")
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Dathlon.md35 ;; The load/store queue unit is not attached to the schedulers but
45 (and (eq_attr "memory" "load,store")
64 ;; imul load/store (2x) fadd fmul fstore
118 (define_reservation "athlon-load" "athlon-agu,
135 (define_reservation "athlon-fpload" "(athlon-fpsched + athlon-load)")
137 (define_reservation "athlon-fploadk8" "(athlon-fpsched + athlon-load)")
175 "athlon-vector,athlon-load,athlon-ieu")
179 "athlon-double,(athlon-ieu+athlon-load)")
183 "athlon-direct,(athlon-ieu+athlon-load)")
187 "athlon-vector,(athlon-ieu+athlon-load)")
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Dbdver3.md27 ;; The load/store queue unit is not attached to the schedulers but
64 (define_reservation "bdver3-load" "bdver3-agu,
83 (define_reservation "bdver3-fpload" "(bdver3-fpsched + bdver3-load)")
144 (eq_attr "memory" "load,both"))))
145 "bdver3-direct,bdver3-load,bdver3-ieu1")
149 (eq_attr "memory" "load,both")))
150 "bdver3-direct,bdver3-load,bdver3-ieu1")
155 (eq_attr "memory" "load,both,store")))
156 "bdver3-vector,bdver3-load,bdver3-ivector")
174 (eq_attr "memory" "load")))
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Dbdver1.md32 ;; The load/store queue unit is not attached to the schedulers but
84 (define_reservation "bdver1-load" "bdver1-agu,
108 (define_reservation "bdver1-fpload" "(bdver1-fpsched + bdver1-load)")
170 (eq_attr "memory" "load,both"))))
171 "bdver1-direct1,bdver1-load,bdver1-ieu1")
175 (eq_attr "memory" "load,both")))
176 "bdver1-direct1,bdver1-load,bdver1-ieu1")
193 (eq_attr "memory" "load,both")))
194 … "bdver1-vector,((bdver1-load,bdver1-ieu0*6)+(bdver1-fpsched,bdver1-fvector))")
202 (eq_attr "memory" "load,both,store")))
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Dglm.md30 ;; MEC has two execution ports - MEC-0 (load) and MEC-1 (store0.
32 (define_cpu_unit "glm-fec-0,glm-fec-1,glm-load,glm-store" "glm")
36 (define_reservation "glm-iec-any-load" "(glm-iec-0|glm-iec-1|glm-iec-2)+glm-load")
38 (define_reservation "glm-iec-any-both" "(glm-iec-0 | glm-iec-1 | glm-iec-2) + glm-load + glm-store")
40 (define_reservation "glm-all" "(glm-iec-0+glm-iec-1+glm-iec-2)+(glm-fec-0+glm-fec-1)+(glm-load+glm-…
42 (define_reservation "glm-int-0-load" "glm-iec-0 + glm-load")
43 (define_reservation "glm-int-0-both" "glm-iec-0 + glm-load + glm-store")
45 (define_reservation "glm-int-1-mem" "glm-iec-1 + glm-load")
47 (define_reservation "glm-int-2-mem" "glm-iec-2 + glm-load")
53 (define_reservation "glm-fmul-4c-mem" "glm-fec-0+glm-load, nothing*3")
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Dpentium.md100 ;; Pentium preserves memory ordering, so when load-execute-store
105 ;; and using conflicting load units together.
112 (define_reservation "pentium-load" "(pentium-load0 | pentium-load1)")
119 (define_reservation "pentium-firstuload" "(pentium-load + pentium-firstu)")
120 (define_reservation "pentium-firstvload" "(pentium-load + pentium-firstv)")
121 (define_reservation "pentium-firstuvload" "(pentium-load + pentium-firstuv)
123 (pentium-load+pentium-firstv))")
124 (define_reservation "pentium-firstuboth" "(pentium-load + pentium-firstu
126 (define_reservation "pentium-firstvboth" "(pentium-load + pentium-firstv
128 (define_reservation "pentium-firstuvboth" "(pentium-load + pentium-firstuv
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/netbsd/src/external/gpl3/binutils/dist/opcodes/
Ds390-opc.txt85 58 l RX_RRRD "load" g5 esa,zarch
86 41 la RX_RRRD "load address" g5 esa,zarch
87 51 lae RX_RRRD "load address extended" g5 esa,zarch
88 9a lam RS_AARD "load access multiple" g5 esa,zarch
89 e500 lasp SSE_RDRD "load address space parameters" g5 esa,zarch
90 23 lcdr RR_FF "load complement (long)" g5 esa,zarch
91 33 lcer RR_FF "load complement (short)" g5 esa,zarch
92 13 lcr RR_RR "load complement" g5 esa,zarch
93 b7 lctl RS_CCRD "load control" g5 esa,zarch
94 68 ld RX_FRRD "load (long)" g5 esa,zarch
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/netbsd/src/external/gpl3/gdb/dist/opcodes/
Ds390-opc.txt85 58 l RX_RRRD "load" g5 esa,zarch
86 41 la RX_RRRD "load address" g5 esa,zarch
87 51 lae RX_RRRD "load address extended" g5 esa,zarch
88 9a lam RS_AARD "load access multiple" g5 esa,zarch
89 e500 lasp SSE_RDRD "load address space parameters" g5 esa,zarch
90 23 lcdr RR_FF "load complement (long)" g5 esa,zarch
91 33 lcer RR_FF "load complement (short)" g5 esa,zarch
92 13 lcr RR_RR "load complement" g5 esa,zarch
93 b7 lctl RS_CCRD "load control" g5 esa,zarch
94 68 ld RX_FRRD "load (long)" g5 esa,zarch
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/netbsd/src/external/bsd/kyua-cli/dist/engine/
Dkyuafile_test.cpp57 const engine::kyuafile suite = engine::kyuafile::load( in ATF_TEST_CASE_BODY()
98 const engine::kyuafile suite = engine::kyuafile::load( in ATF_TEST_CASE_BODY()
145 const engine::kyuafile suite = engine::kyuafile::load( in ATF_TEST_CASE_BODY()
189 const engine::kyuafile suite = engine::kyuafile::load( in ATF_TEST_CASE_BODY()
225 const engine::kyuafile suite = engine::kyuafile::load( in ATF_TEST_CASE_BODY()
266 const engine::kyuafile suite = engine::kyuafile::load( in ATF_TEST_CASE_BODY()
300 engine::kyuafile::load(fs::path("config"), none)); in ATF_TEST_CASE_BODY()
309 ATF_REQUIRE_THROW(engine::load_error, engine::kyuafile::load( in ATF_TEST_CASE_BODY()
320 engine::kyuafile::load(fs::path("config"), none)); in ATF_TEST_CASE_BODY()
328 (void)engine::kyuafile::load(fs::path("config"), none); in ATF_TEST_CASE_BODY()
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/netbsd/src/crypto/external/bsd/openssl/lib/libcrypto/arch/arm/
Dchacha-armv4.S67 ldmia r12,{r4,r5,r6,r7} @ load counter and nonce
68 sub sp,sp,#4*(16) @ off-load area
71 ldmia r3,{r4,r5,r6,r7,r8,r9,r10,r11} @ load key
72 ldmia r14,{r0,r1,r2,r3} @ load sigma
75 str r10,[sp,#4*(16+10)] @ off-load "rx"
76 str r11,[sp,#4*(16+11)] @ off-load "rx"
81 ldmia sp,{r0,r1,r2,r3,r4,r5,r6,r7,r8,r9} @ load key material
87 ldr r12,[sp,#4*(12)] @ modulo-scheduled load
207 ldr r11,[sp,#4*(32+2)] @ load len
223 ldrhs r12,[sp,#4*(32+1)] @ ... load inp
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/netbsd/src/crypto/external/bsd/heimdal/dist/lib/hcrypto/
Ddes.c328 load(const unsigned char *b, uint32_t v[2]) in load() function
387 load(*input, u); in DES_ecb_encrypt()
416 load(*iv, uiv); in DES_cbc_encrypt()
420 load(input, u); in DES_cbc_encrypt()
434 load(tmp, u); in DES_cbc_encrypt()
442 load(input, u); in DES_cbc_encrypt()
457 load(tmp, u); in DES_cbc_encrypt()
492 load(*iv, uiv); in DES_pcbc_encrypt()
497 load(input, u); in DES_pcbc_encrypt()
512 load(tmp, u); in DES_pcbc_encrypt()
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/netbsd/src/sys/arch/mips/mips/
Dspl.S72 NOP_L # load delay
74 NOP_L # load delay
93 NOP_L # load delay
105 MFC0_HAZARD # load delay
121 NOP_L # load delay
123 NOP_L # load delay
134 INT_L a1, (v1) # load SR bits for this IPL
160 INT_L a1, (v1) # load SR bits for this IPL
162 MFC0_HAZARD # load delay
178 MFC0_HAZARD # load delay
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/netbsd/src/games/sail/
Dpl_3.c55 int load; in acceptcombat() local
79 load = mf->loadR; in acceptcombat()
84 load = mf->loadL; in acceptcombat()
88 if ((!guns && !car) || load == L_EMPTY || in acceptcombat()
99 if (target > rangeofshot[load] || (!guns && target >= 3)) in acceptcombat()
103 if (load > L_CHAIN && target < 6) { in acceptcombat()
171 hit += AMMO[index][load - 1]; in acceptcombat()
180 if (load == L_GRAPE) in acceptcombat()
194 if (load == L_CHAIN) { in acceptcombat()
199 table(ms, closest, shootat, load, hit, roll); in acceptcombat()
Dpl_6.c148 int loadL, loadR, ready, load; in loadplayer() local
169 load = L_ROUND; in loadplayer()
173 load = L_DOUBLE; in loadplayer()
177 load = L_CHAIN; in loadplayer()
181 load = L_GRAPE; in loadplayer()
189 mf->loadR = load; in loadplayer()
192 mf->loadL = load; in loadplayer()
/netbsd/src/external/gpl3/gdb/dist/include/opcode/
Dwasm.h56 WASM_OPCODE (0x28, "i32.load", i32, i32, load, agnostic)
57 WASM_OPCODE (0x29, "i64.load", i32, i64, load, agnostic)
58 WASM_OPCODE (0x2a, "f32.load", i32, f32, load, agnostic)
59 WASM_OPCODE (0x2b, "f64.load", i32, f64, load, agnostic)
60 WASM_OPCODE (0x2c, "i32.load8_s", i32, i32, load, signed)
61 WASM_OPCODE (0x2d, "i32.load8_u", i32, i32, load, unsigned)
62 WASM_OPCODE (0x2e, "i32.load16_s", i32, i32, load, signed)
63 WASM_OPCODE (0x2f, "i32.load16_u", i32, i32, load, unsigned)
64 WASM_OPCODE (0x30, "i64.load8_s", i32, i64, load, signed)
65 WASM_OPCODE (0x31, "i64.load8_u", i32, i64, load, unsigned)
[all …]
/netbsd/src/external/gpl3/binutils/dist/include/opcode/
Dwasm.h56 WASM_OPCODE (0x28, "i32.load", i32, i32, load, agnostic)
57 WASM_OPCODE (0x29, "i64.load", i32, i64, load, agnostic)
58 WASM_OPCODE (0x2a, "f32.load", i32, f32, load, agnostic)
59 WASM_OPCODE (0x2b, "f64.load", i32, f64, load, agnostic)
60 WASM_OPCODE (0x2c, "i32.load8_s", i32, i32, load, signed)
61 WASM_OPCODE (0x2d, "i32.load8_u", i32, i32, load, unsigned)
62 WASM_OPCODE (0x2e, "i32.load16_s", i32, i32, load, signed)
63 WASM_OPCODE (0x2f, "i32.load16_u", i32, i32, load, unsigned)
64 WASM_OPCODE (0x30, "i64.load8_s", i32, i64, load, signed)
65 WASM_OPCODE (0x31, "i64.load8_u", i32, i64, load, unsigned)
[all …]
/netbsd/src/tests/modules/
Dt_modctl.c57 static int load(prop_dictionary_t, bool, const char *, ...);
269 load(prop_dictionary_t props, bool fatal, const char *fmt, ...) in load() function
361 ATF_CHECK(load(NULL, false, " ") == ENOENT); in ATF_TC_BODY()
362 ATF_CHECK(load(NULL, false, "non-existent.o") == ENOENT); in ATF_TC_BODY()
367 ATF_CHECK(load(NULL, false, "%s", longname) == ENAMETOOLONG); in ATF_TC_BODY()
370 load(NULL, true, "%s/k_helper/k_helper.kmod", in ATF_TC_BODY()
393 load(props, true, "%s/k_helper/k_helper.kmod", in ATF_TC_BODY()
408 load(props, true, "%s/k_helper/k_helper.kmod", in ATF_TC_BODY()
428 load(props, true, "%s/k_helper/k_helper.kmod", in ATF_TC_BODY()
467 load(props, true, "%s/k_helper/k_helper.kmod", in ATF_TC_BODY()
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/netbsd/src/external/gpl3/gcc/dist/gcc/config/rs6000/
Dpower6.md87 ; The default for a value written by a fixed point load
89 (define_insn_reservation "power6-load" 2 ; fx
90 (and (eq_attr "type" "load")
97 ; by a fixed point load is used as the source value on
99 (define_bypass 1 "power6-load,\
100 power6-load-update,\
101 power6-load-update-indexed"
109 (define_insn_reservation "power6-load-ext" 4 ; fx
110 (and (eq_attr "type" "load")
117 ; by a fixed point load ext is used as the source value on
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Dpcrel-opt.md53 ;; The marker is an integer constant that links the load of the external
54 ;; address to the load of the actual variable.
59 ;; we will ultimately do the load into, so we use DImode. We just need to mark
115 (set_attr "type" "load")
119 ;; as the final load.
128 (set_attr "type" "load")
141 ;; PCREL_OPT load operation of GPRs. Operand 4 (the register used to hold the
143 ;; the normal load.
159 [(set_attr "type" "load")])
161 ;; PCREL_OPT load with sign/zero extension
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