| /netbsd/src/external/gpl3/gdb/dist/sim/frv/ |
| D | cache.c | 87 cache->pipeline[i].requests = NULL; in frv_cache_init()
88 cache->pipeline[i].status.flush.valid = 0; in frv_cache_init()
89 cache->pipeline[i].status.return_buffer.valid = 0; in frv_cache_init()
90 cache->pipeline[i].status.return_buffer.data in frv_cache_init()
93 cache->pipeline[i].stages[j].request = NULL; in frv_cache_init()
110 free (cache->pipeline[LS].status.return_buffer.data); in frv_cache_term()
111 free (cache->pipeline[LD].status.return_buffer.data); in frv_cache_term()
461 memcpy (cache->pipeline[pipe].status.return_buffer.data, in copy_line_to_return_buffer()
463 cache->pipeline[pipe].status.return_buffer.address in copy_line_to_return_buffer()
465 cache->pipeline[pipe].status.return_buffer.valid = 1; in copy_line_to_return_buffer()
[all …]
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| D | cache.h | 175 FRV_CACHE_PIPELINE pipeline[2]; /* Cache pipelines. */ member
203 T2H_##N (*(mode *)(& (cache)->pipeline[slot].status.return_buffer.data \
207 ((void *)& (cache)->pipeline[slot].status.return_buffer.data[(address) \
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| /netbsd/src/external/gpl3/gcc/dist/gcc/config/arm/ |
| D | cortex-a9.md | 1 ;; ARM Cortex-A9 pipeline description
27 ;; The Cortex-A9 core is modelled as a dual issue pipeline that has
30 ;; 2. P0 / main pipeline for data processing instructions.
31 ;; 3. P1 / Dual pipeline for Data processing instructions.
32 ;; 4. MAC pipeline for multiply as well as multiply
35 ;; The Load/Store, VFP and Neon issue pipeline are multiplexed.
36 ;; The P0 / main pipeline and M1 stage of the MAC pipeline are
38 ;; The P1 / dual pipeline and M2 stage of the MAC pipeline are
74 ;; Issue at the same time along the load store pipeline and
75 ;; the VFP / Neon pipeline is not possible.
[all …]
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| D | vfp11.md | 1 ;; ARM VFP11 pipeline description
25 ;; - A 8-stage FMAC pipeline (7 execute + writeback) with forward from
28 ;; - A 5-stage DS pipeline (4 execute + writeback) for divide/sqrt insns.
29 ;; These insns also uses first execute stage of FMAC pipeline.
31 ;; - A 4-stage LS pipeline (execute + 2 memory + writeback) with forward from
36 ;; to model the first stage of each pipeline
37 ;; ??? Need to model LS pipeline properly for load/store multiple?
78 ;; Moves to/from arm regs also use the load/store pipeline.
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| D | cortex-a5.md | 1 ;; ARM Cortex-A5 pipeline description
27 ;; The integer (ALU) pipeline. There are five DPU pipeline
36 ;; The branch pipeline. Branches can dual-issue with other instructions
41 ;; Pseudo-unit for blocking the multiply pipeline when a double-precision
46 ;; The floating-point add pipeline (ex1/f1 stage), used to model the usage
47 ;; of the add pipeline by fmac instructions, etc.
90 ;; The multiplier pipeline can forward results from wr stage only so
196 ;; processing the instruction), but the usage of the FP add pipeline could
228 ;; result to travel down the multiply pipeline, or not. Assuming so. (If
232 ;; multiply pipeline to collect the divide/square-root result.
[all …]
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| D | cortex-a15.md | 1 ;; ARM Cortex-A15 pipeline description
24 ;; The Cortex-A15 core is modelled as a triple issue pipeline that has
28 ;; 3. One pipeline for branch operations: BX
29 ;; 4. One pipeline for integer multiply and divide operations: MX
52 ;; The extended load-store pipeline
55 ;; The extended ALU pipeline
77 ;; core reuses the Cortex-A15 pipeline description for the moment.
167 ;; pipeline. The result however is available the next cycle.
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| D | arm1026ejs.md | 26 ;; This automaton provides a pipeline description for the ARM
41 ;; - An Arithmetic Logic Unit (ALU) pipeline.
43 ;; The ALU pipeline has fetch, issue, decode, execute, memory, and
47 ;; - A Load-Store Unit (LSU) pipeline.
49 ;; The LSU pipeline has decode, execute, memory, and write stages.
60 ;; pipeline in each of the three stages. The results are available
169 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
190 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
200 ;; The ALU pipeline is stalled until the completion of the last memory
201 ;; stage in the LSU pipeline. That is modeled by keeping the ALU
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| D | cortex-a7.md | 1 ;; ARM Cortex-A7 pipeline description
68 ;; The Cortex-A7 pipeline integer and vfp pipeline.
85 ;; Pseudo-unit for blocking the multiply pipeline when a double-precision
90 ;; The floating-point add pipeline (ex1/f1 stage), used to model the usage
91 ;; of the add pipeline by fmac instructions, etc.
167 ;; The multiplier pipeline can forward results from wr stage only so
195 ;; and occupy only one pipeline stage.
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| D | arm1020e.md | 26 ;; This automaton provides a pipeline description for the ARM
41 ;; - An Arithmetic Logic Unit (ALU) pipeline.
43 ;; The ALU pipeline has fetch, issue, decode, execute, memory, and
47 ;; - A Load-Store Unit (LSU) pipeline.
49 ;; The LSU pipeline has decode, execute, memory, and write stages.
60 ;; pipeline in each of the three stages. The results are available
169 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
190 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
200 ;; The ALU pipeline is decoupled after the first cycle unless there is
325 ;; Moves to/from arm regs also use the load/store pipeline.
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| D | arm1136jfs.md | 26 ;; This automaton provides a pipeline description for the ARM
41 ;; - A 4-stage decode pipeline, shared by all three. It has fetch (1),
45 ;; - A 4-stage ALU pipeline. It has shifter, ALU (main integer operations),
48 ;; - A 4-stage multiply-accumulate pipeline. It has three stages, called
52 ;; which operate in lockstep. Results from either pipeline will be
54 ;; in lockstep, we schedule them as a single "execute" pipeline.
56 ;; - A 4-stage LSU pipeline. It has address generation, data cache (1),
57 ;; data cache (2), and writeback stages. (Note that this pipeline,
69 ;; pipeline in each of the eight stages. The results are available
199 ;; pass through the pipeline and make the result available after three
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| D | fa626te.md | 24 ;; Modeled pipeline characteristics:
34 ;; This automaton provides a pipeline description for the Faraday
47 ;; There is a single pipeline
49 ;; The ALU pipeline has fetch, decode, execute, memory, and
62 ;; pipeline in each of the three stages. The results are available
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| D | fa526.md | 24 ;; Modeled pipeline characteristics:
28 ;; This automaton provides a pipeline description for the Faraday
41 ;; There is a single pipeline
43 ;; The ALU pipeline has fetch, decode, execute, memory, and
56 ;; pipeline in each of the three stages. The results are available
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| D | fa606te.md | 24 ;; Modeled pipeline characteristics:
28 ;; This automaton provides a pipeline description for the Faraday
41 ;; There is a single pipeline
43 ;; The ALU pipeline has fetch, decode, execute, memory, and
56 ;; pipeline in each of the three stages. The results are available
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| D | cortex-a15-neon.md | 1 ;; ARM Cortex-A15 NEON pipeline description
221 ;; The 32x32 integer multiply-accumulate pipeline.
226 ;; The 64-bit ALU pipeline.
235 ;; Integer shift pipeline.
239 ;; SIMD multiply pipeline.
251 ;; SIMD ALU pipeline.
263 ;; SIMD multiply-accumulate pipeline.
278 ;; Vector FP multiply pipeline
283 ;; Load permute pipeline
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| D | arm926ejs.md | 26 ;; This automaton provides a pipeline description for the ARM
39 ;; There is a single pipeline
41 ;; The ALU pipeline has fetch, decode, execute, memory, and
52 ;; pipeline in each of the three stages. The results are available
91 ;; stages of the pipeline
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| D | fmp626.md | 31 ;; This automaton provides a pipeline description for the Faraday
44 ;; There is a single pipeline
46 ;; The ALU pipeline has fetch, decode, execute, memory, and
57 ;; pipeline in each of the three stages. The results are available
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| /netbsd/src/crypto/external/bsd/openssl/dist/test/ |
| D | sslbuffertest.c | 182 int i, pipeline = test > 3; in test_free_buffers() local
185 if (pipeline) { in test_free_buffers()
196 if (pipeline) { in test_free_buffers()
212 for (i = 0; i <= pipeline; i++) { in test_free_buffers()
226 if (pipeline) in test_free_buffers()
258 if (pipeline) { in test_free_buffers()
280 if (pipeline) { in test_free_buffers()
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| /netbsd/src/external/gpl3/gdb/dist/gdb/testsuite/gdb.base/ |
| D | gnu-debugdata.exp | 34 proc pipeline {test args} { procedure
68 if {[pipeline "nm -D" \
79 if {[pipeline "nm" \
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| /netbsd/src/external/gpl3/gcc/dist/libiberty/ |
| D | pexecute.txh | 7 independent interface to execute a pipeline.
38 Execute one program in a pipeline. On success this returns
50 This must be set on the last program in the pipeline. In particular,
88 flag can be specified only on the last program in pipeline.
150 Execute one program in a pipeline, permitting the environment for the
165 the pipeline as input.
183 the first program in the pipeline; @var{fp} is opened for writing.
188 finished writing data to the pipeline.
209 before starting the first process in the pipeline, consider using
215 program in the pipeline is waiting for the next to read more data, and
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| /netbsd/src/external/gpl3/binutils/dist/libiberty/ |
| D | pexecute.txh | 7 independent interface to execute a pipeline.
38 Execute one program in a pipeline. On success this returns
50 This must be set on the last program in the pipeline. In particular,
88 flag can be specified only on the last program in pipeline.
150 Execute one program in a pipeline, permitting the environment for the
165 the pipeline as input.
183 the first program in the pipeline; @var{fp} is opened for writing.
188 finished writing data to the pipeline.
209 before starting the first process in the pipeline, consider using
215 program in the pipeline is waiting for the next to read more data, and
[all …]
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| /netbsd/src/external/gpl3/gdb/dist/libiberty/ |
| D | pexecute.txh | 7 independent interface to execute a pipeline.
38 Execute one program in a pipeline. On success this returns
50 This must be set on the last program in the pipeline. In particular,
88 flag can be specified only on the last program in pipeline.
150 Execute one program in a pipeline, permitting the environment for the
165 the pipeline as input.
183 the first program in the pipeline; @var{fp} is opened for writing.
188 finished writing data to the pipeline.
209 before starting the first process in the pipeline, consider using
215 program in the pipeline is waiting for the next to read more data, and
[all …]
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| /netbsd/src/sys/arch/mips/mips/ |
| D | cache_r3k_subr.S | 101 # 4 cycles to pipeline to drain.
169 # 4 cycles to wait for pipeline to drain.
213 # 4 cycles to wait for pipeline to drain.
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| /netbsd/src/bin/sh/ |
| D | nodetypes | 63 NPIPE npipe # a pipeline
65 backgnd int # set to run pipeline in background
66 cmdlist nodelist # the commands in the pipeline
148 NNOT nnot # ! command (actually pipeline)
149 NDNOT nnot # ! ! pipeline (optimisation)
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| /netbsd/src/external/gpl3/gcc/dist/gcc/config/s390/ |
| D | 2064.md | 28 ;; z900 (cpu 2064) pipeline
116 ;; to the address generation pipeline stage.
124 ;; result back to the address generation pipeline stage.
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| /netbsd/src/external/lgpl3/gmp/dist/mpn/x86_64/ |
| D | README | 60 Pentium4 for the GMP loops. Its integer pipeline is somewhat similar to to
61 the Opteron/Athlon64 pipeline, except that the GMP favourites ADC/SBB and
63 pipeline stall of around 10 cycles. The default mpn_add_n and mpn_sub_n
|