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Searched refs:psr (Results 1 – 25 of 106) sorted by relevance

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/netbsd/src/external/gpl3/gdb/dist/sim/erc32/
Dexec.c221 static uint32_t sub_cc (uint32_t psr, int32_t operand1, int32_t operand2,
223 static uint32_t add_cc (uint32_t psr, int32_t operand1, int32_t operand2,
239 sub_cc(uint32_t psr, int32_t operand1, int32_t operand2, int32_t result) in sub_cc() argument
241 psr = ((psr & ~PSR_N) | ((result >> 8) & PSR_N)); in sub_cc()
243 psr &= ~PSR_Z; in sub_cc()
245 psr |= PSR_Z; in sub_cc()
246 psr = (psr & ~PSR_V) | ((((operand1 & ~operand2 & ~result) | in sub_cc()
248 psr = (psr & ~PSR_C) | ((((~operand1 & operand2) | in sub_cc()
250 return psr; in sub_cc()
254 add_cc(uint32_t psr, int32_t operand1, int32_t operand2, int32_t result) in add_cc() argument
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Dinterf.c83 if (sregs->psr & 0x080) in run_sim()
98 sregs->r[(((sregs->psr & 7) << 4) + 14) & 0x7f], in run_sim()
99 sregs->r[(((sregs->psr & 7) << 4) + 30) & 0x7f], in run_sim()
101 sregs->psr & 7, in run_sim()
408 cwp = sregs.psr & PSR_CWP; in flush_windows()
/netbsd/src/external/gpl3/gdb/dist/sim/arm/
Diwmmxt.c1277 ARMword psr = 0; in WADD() local
1308 SIMD8_SET (psr, NBIT8 (s), SIMD_NBIT, i); in WADD()
1309 SIMD8_SET (psr, ZBIT8 (s), SIMD_ZBIT, i); in WADD()
1310 SIMD8_SET (psr, carry, SIMD_CBIT, i); in WADD()
1311 SIMD8_SET (psr, overflow, SIMD_VBIT, i); in WADD()
1318 SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i); in WADD()
1319 SIMD8_SET (psr, ZBIT8 (x), SIMD_ZBIT, i); in WADD()
1322 SIMD8_SET (psr, carry, SIMD_CBIT, i); in WADD()
1323 SIMD8_SET (psr, overflow, SIMD_VBIT, i); in WADD()
1331 SIMD8_SET (psr, NBIT8 (x), SIMD_NBIT, i); in WADD()
[all …]
/netbsd/src/sys/arch/sparc/include/
Dpsl.h248 int psr; in getpsr() local
250 __asm volatile("rd %%psr,%0" : "=r" (psr)); in getpsr()
251 return (psr); in getpsr()
273 int psr, oldipl; in spl0() local
280 __asm volatile("rd %%psr,%0" : "=r" (psr) : : "memory"); in spl0()
281 oldipl = psr & PSR_PIL; in spl0()
282 __asm volatile("wr %0,%1,%%psr" : : "r" (psr), "r" (oldipl)); in spl0()
299 int psr; \
300 __asm volatile("rd %%psr,%0" : "=r" (psr)); \
301 psr &= ~PSR_PIL; \
[all …]
/netbsd/src/sys/arch/ia64/stand/efi/libefi/
Dexec.c99 u_int64_t psr; in disable_ic() local
100 __asm __volatile("mov %0=psr;;" : "=r" (psr)); in disable_ic()
102 return psr; in disable_ic()
106 restore_ic(u_int64_t psr) in restore_ic() argument
108 __asm __volatile("mov psr.l=%0;; srlz.i" :: "r" (psr)); in restore_ic()
117 u_int64_t psr; in enter_kernel() local
138 u_int64_t psr; in elf64_exec() local
179 psr = disable_ic(); in elf64_exec()
209 restore_ic(psr); in elf64_exec()
/netbsd/src/sys/arch/ia64/ia64/
Dtrap.c227 printpsr(uint64_t psr) in printpsr() argument
229 printbits(psr, psr_bits, sizeof(psr_bits)/sizeof(psr_bits[0])); in printpsr()
264 printf(" cr.ipsr = 0x%lx (", tf->tf_special.psr); in printtrap()
265 printpsr(tf->tf_special.psr); in printtrap()
271 if (tf->tf_special.psr & IA64_PSR_IS) { in printtrap()
301 slot = ((tf->tf_special.psr & IA64_PSR_RI) == IA64_PSR_RI_0) ? 0 : in trap_decode_break()
302 ((tf->tf_special.psr & IA64_PSR_RI) == IA64_PSR_RI_1) ? 1 : 2; in trap_decode_break()
520 tf->tf_special.psr &= ~IA64_PSR_SS; in trap()
592 tf->tf_special.psr &= ~IA64_PSR_RI; in trap()
615 tf->tf_special.psr &= ~IA64_PSR_RI; in trap()
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Dpal.S59 mov psrsave=psr
71 rsm psr.i // disable interrupts
74 2: mov psr.l=psrsave
155 mov psrsave=psr
166 rsm psr.i // disable interrupts
169 mov psr.l=psrsave
Dmachdep.c268 uint64_t psr; in map_vhpt() local
283 __asm __volatile("mov %0=psr" : "=r"(psr)); in map_vhpt()
290 __asm __volatile("mov psr.l=%0" :: "r" (psr)); in map_vhpt()
298 uint64_t psr; in map_pal_code() local
311 __asm __volatile("mov %0=psr" : "=r"(psr)); in map_pal_code()
322 __asm __volatile("mov psr.l=%0" :: "r" (psr)); in map_pal_code()
330 uint64_t psr; in map_gateway_page() local
339 __asm __volatile("mov %0=psr" : "=r"(psr)); in map_gateway_page()
348 __asm __volatile("mov psr.l=%0" :: "r" (psr)); in map_gateway_page()
789 tf->tf_special.psr = IA64_PSR_IC | IA64_PSR_I | IA64_PSR_IT | in setregs()
Dexception.S305 rsm psr.dt
547 ssm psr.dt|psr.ic|psr.dfh
567 rsm psr.i
576 rsm psr.dt|psr.ic
754 ssm psr.dt
817 (p11) ssm psr.i ; \
890 1: rsm psr.dt // turn off data translations
934 ssm psr.dt
945 9: ssm psr.dt
976 1: rsm psr.dt // turn off data translations
[all …]
Ddb_interface.c165 slot = (f->tf_special.psr >> 41) & 3; in db_getip()
175 f->tf_special.psr &= ~IA64_PSR_RI; in db_getip()
176 f->tf_special.psr |= slot << 41; in db_getip()
233 {"psr", DB_OFFSET(tf_special.psr), db_frame},
428 regs->tf_special.psr += IA64_PSR_RI_1; in db_pc_advance()
429 if ((regs->tf_special.psr & IA64_PSR_RI) > IA64_PSR_RI_2) { in db_pc_advance()
430 regs->tf_special.psr &= ~IA64_PSR_RI; in db_pc_advance()
Dsyscall_stubs.S92 mov r11=psr
97 rum psr.be
385 ssm psr.dfh|psr.ac
512 mov psr.l=r26
574 mov psr.l=r26
/netbsd/src/sys/arch/sparc/sparc/
Dlock_stubs.s130 rd %psr, %o1
137 wr %o2, %o1, %psr
177 rd %psr, %o1
179 wr %o3, %o1, %psr
200 rd %psr, %o4 ! disable interrupts
202 wr %o5, 0, %psr
225 wr %o4, 0, %psr ! enable interrupts
233 wr %o4, 0, %psr ! enable interrupts
Dlocore.s297 mov (type), %l3; b label; mov %psr, %l0; nop
301 mov (lev), %l3; b _C_LABEL(sparc_interrupt44c); mov %psr, %l0; nop
305 mov (lev), %l3; b _C_LABEL(sparc_interrupt4m); mov %psr, %l0; nop
310 mov (lev), %l3; mov (bit), %l4; b softintr_sun44c; mov %psr, %l0
333 #define SYSCALL b _C_LABEL(_syscall); mov %psr, %l0; nop; nop
334 #define WINDOW_OF b window_of; mov %psr, %l0; nop; nop
335 #define WINDOW_UF b window_uf; mov %psr, %l0; nop; nop
337 #define ZS_INTERRUPT b zshard; mov %psr, %l0; nop; nop
368 TRAP(T_FPDISABLED) ! 04 = fp instr, but EF bit off in psr
400 TRAP(T_CPDISABLED) ! 24 = coprocessor instr, EC bit off in psr
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Dtrap.c222 trap(unsigned type, int psr, int pc, struct trapframe *tf) in trap() argument
241 if (psr & PSR_PS) { in trap()
297 snprintb(bits, sizeof(bits), PSR_BITS, psr); in trap()
335 snprintb(bits, sizeof(bits), PSR_BITS, psr); in trap()
759 mem_access_fault(unsigned type, int ser, u_int v, int pc, int psr, in mem_access_fault() argument
826 if (psr & PSR_PS) { in mem_access_fault()
922 if (psr & PSR_PS) { in mem_access_fault()
965 if ((psr & PSR_PS) == 0) { in mem_access_fault()
978 int pc, psr; in mem_access_fault4m() local
1013 psr = tf->tf_psr; in mem_access_fault4m()
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/netbsd/src/sys/arch/arm/include/
Dlocore.h123 #define VALID_PSR(psr) \ argument
124 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & I32_bit) == 0)
126 #define VALID_PSR(psr) \ argument
127 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & IF32_bits) == 0)
/netbsd/src/sys/arch/sparc/stand/common/
Dsrt0.S94 wr %g0, 0, %wim ! make sure we can set psr
96 wr %g0, PSR_S|PSR_PS|PSR_PIL, %psr ! set initial psr
100 rd %psr, %l0
101 wr %l0, PSR_ET, %psr
134 rd %psr, %o0
136 wr %o0, 0xb00, %psr ! (11 << 8)
/netbsd/src/sys/arch/ia64/stand/ia64/ski/
Dssc.c49 register u_int64_t psr; in ssc() local
52 __asm __volatile("mov %0=psr;;" : "=r"(psr)); in ssc()
57 __asm __volatile("mov psr.l=%0;; srlz.d" :: "r"(psr)); in ssc()
/netbsd/src/sys/arch/ia64/include/
Ddb_machdep.h56 … ((db_addr_t)(regs)->tf_special.iip + (((regs)->tf_special.psr>>41) & 3))
60 #define PC_REGS(regs) ((db_addr_t)(regs)->tf_special.iip + (((regs)->tf_special.psr>>41) & 3))
63 #define db_set_single_step(regs) ((regs)->tf_special.psr |= IA64_PSR_SS)
64 #define db_clear_single_step(regs) ((regs)->tf_special.psr &= ~IA64_PSR_SS)
Dcpufunc.h214 register_t psr; in intr_disable() local
216 __asm __volatile ("mov %0=psr;;" : "=r"(psr)); in intr_disable()
218 return (psr & IA64_PSR_I) ? 1 : 0; in intr_disable()
/netbsd/src/external/gpl3/gdb/dist/gdb/
Dia64-linux-nat.c538 ULONGEST psr; in enable_watchpoints_in_psr() local
540 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr); in enable_watchpoints_in_psr()
541 if (!(psr & IA64_PSR_DB)) in enable_watchpoints_in_psr()
543 psr |= IA64_PSR_DB; /* Set the db bit - this enables hardware in enable_watchpoints_in_psr()
545 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr); in enable_watchpoints_in_psr()
693 CORE_ADDR psr; in stopped_data_address() local
704 regcache_cooked_read_unsigned (regcache, IA64_PSR_REGNUM, &psr); in stopped_data_address()
705 psr |= IA64_PSR_DD; /* Set the dd bit - this will disable the watchpoint in stopped_data_address()
707 regcache_cooked_write_unsigned (regcache, IA64_PSR_REGNUM, psr); in stopped_data_address()
Dsparc-linux-tdep.c258 ULONGEST psr; in sparc_linux_write_pc() local
271 regcache_cooked_read_unsigned (regcache, SPARC32_PSR_REGNUM, &psr); in sparc_linux_write_pc()
272 psr &= ~PSR_SYSCALL; in sparc_linux_write_pc()
273 regcache_cooked_write_unsigned (regcache, SPARC32_PSR_REGNUM, psr); in sparc_linux_write_pc()
/netbsd/src/sys/arch/evbppc/obs405/
Dobs200_machdep.c124 u_int32_t psr __debugused; in initppc()
131 psr = mfdcr(DCR_CPC0_PSR); in initppc()
152 printf(" Chip Pin Strapping Register = 0x%08x\n", psr); in initppc()
/netbsd/src/external/gpl3/gdb/dist/sim/frv/
Dtraps.c348 USI psr = GET_PSR (); in frv_rett() local
351 SET_PSR_ET (psr, 1); in frv_rett()
352 SET_PSR_S (psr, GET_PSR_PS (psr)); in frv_rett()
353 sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr); in frv_rett()
357 USI psr = GET_PSR (); in frv_rett() local
360 SET_PSR_ET (psr, GET_H_BPSR_BET ()); in frv_rett()
361 SET_PSR_S (psr, GET_H_BPSR_BS ()); in frv_rett()
362 sim_queue_fn_si_write (current_cpu, frvbf_h_spr_set, H_SPR_PSR, psr); in frv_rett()
/netbsd/src/common/lib/libc/arch/sparc/atomic/
Datomic_cas.S42 rd %psr, %o4 /* disable interrupts */;\
44 wr %o5, 0, %psr ;\
50 wr %o4, 0, %psr /* enable interrupts */ ;\
/netbsd/src/external/gpl3/gdb/dist/gdb/stubs/
Dsparc-stub.c668 unsigned long *newsp, psr; in handle_exception() local
670 psr = registers[PSR]; in handle_exception()
687 if (psr != registers[PSR]) in handle_exception()
688 registers[PSR] = (psr & 0x1f) | (registers[PSR] & ~0x1f); in handle_exception()

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