| /netbsd/src/sys/arch/mips/atheros/dev/ |
| D | if_ae.c | 671 sc->sc_txdescs[nexttx].ad_status = in ae_start()
673 sc->sc_txdescs[nexttx].ad_bufaddr1 = in ae_start()
675 sc->sc_txdescs[nexttx].ad_ctl = in ae_start()
686 sc->sc_txdescs[sc->sc_txnext].ad_ctl |= ADCTL_Tx_FS; in ae_start()
687 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_LS; in ae_start()
695 sc->sc_txdescs[seg].ad_status); in ae_start()
697 sc->sc_txdescs[seg].ad_ctl); in ae_start()
699 sc->sc_txdescs[seg].ad_bufaddr1); in ae_start()
701 sc->sc_txdescs[seg].ad_bufaddr2); in ae_start()
742 sc->sc_txdescs[lasttx].ad_ctl |= ADCTL_Tx_IC; in ae_start()
[all …]
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| D | aevar.h | 171 #define sc_txdescs sc_control_data->acd_txdescs macro
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| /netbsd/src/sys/dev/pci/ |
| D | if_pcn.c | 263 #define sc_txdescs sc_control_data->pcd_txdescs macro
1051 sc->sc_txdescs[nexttx].tmd0 = 0; in pcn_start()
1052 sc->sc_txdescs[nexttx].tmd2 = in pcn_start()
1054 sc->sc_txdescs[nexttx].tmd1 = in pcn_start()
1071 sc->sc_txdescs[nexttx].tmd0 = in pcn_start()
1073 sc->sc_txdescs[nexttx].tmd2 = 0; in pcn_start()
1074 sc->sc_txdescs[nexttx].tmd1 = in pcn_start()
1086 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_LTINT); in pcn_start()
1089 sc->sc_txdescs[lasttx].tmd1 |= htole32(LE_T1_ENP); in pcn_start()
1090 sc->sc_txdescs[sc->sc_txnext].tmd1 |= in pcn_start()
[all …]
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| D | if_dge.c | 281 #define sc_txdescs sc_control_data->wcd_txdescs macro
1154 t = (struct dge_ctdes *)&sc->sc_txdescs[sc->sc_txnext];
1333 sc->sc_txdescs[nexttx].dt_baddrh =
1335 sc->sc_txdescs[nexttx].dt_baddrl =
1337 sc->sc_txdescs[nexttx].dt_ctl =
1339 sc->sc_txdescs[nexttx].dt_status = 0;
1340 sc->sc_txdescs[nexttx].dt_popts = cksumfields;
1341 sc->sc_txdescs[nexttx].dt_vlan = 0;
1359 sc->sc_txdescs[lasttx].dt_ctl |=
1366 lasttx, le32toh(sc->sc_txdescs[lasttx].dt_ctl)));
[all …]
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| D | if_kse.c | 247 #define sc_txdescs sc_control_data->kcd_txdescs macro
723 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); in kse_init()
725 sc->sc_txdescs[i].t3 = paddr; in kse_init()
728 sc->sc_txdescs[KSE_NTXDESC - 1].t3 = KSE_CDTXADDR(sc, 0); in kse_init()
989 struct tdes *tdes = &sc->sc_txdescs[nexttx]; in kse_start()
1014 sc->sc_txdescs[lasttx].t1 |= T1_IC; in kse_start()
1020 sc->sc_txdescs[lasttx].t1 |= T1_LS; in kse_start()
1021 sc->sc_txdescs[sc->sc_txnext].t1 |= T1_FS; in kse_start()
1022 sc->sc_txdescs[sc->sc_txnext].t0 = T0_OWN; in kse_start()
1304 txstat = sc->sc_txdescs[txs->txs_lastdesc].t0; in txreap()
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| D | if_ste.c | 144 #define sc_txdescs sc_control_data->scd_txdescs macro
686 tfd = &sc->sc_txdescs[nexttx]; in ste_start()
792 sc->sc_txdescs[sc->sc_txlast].tfd_next = 0; in ste_start()
793 sc->sc_txdescs[sc->sc_txlast].tfd_control |= in ste_start()
802 sc->sc_txdescs[olasttx].tfd_next = in ste_start()
1004 control = le32toh(sc->sc_txdescs[i].tfd_control); in ste_txintr()
1243 control = le32toh(sc->sc_txdescs[id].tfd_control); in ste_txrestart()
1245 sc->sc_txdescs[id].tfd_control = htole32(control); in ste_txrestart()
1285 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); in ste_init()
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| D | if_stge.c | 157 #define sc_txdescs sc_control_data->scd_txdescs macro
876 tfd = &sc->sc_txdescs[nexttx]; in stge_start()
1206 control = le64toh(sc->sc_txdescs[i].tfd_control); in stge_txintr()
1532 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); in stge_init()
1534 sc->sc_txdescs[i].tfd_next = htole64( in stge_init()
1536 sc->sc_txdescs[i].tfd_control = htole64(TFD_TFDDone); in stge_init()
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| D | if_vge.c | 216 #define sc_txdescs sc_control_data->vcd_txdescs macro
1376 txstat = le32toh(sc->sc_txdescs[idx].td_sts); in vge_txeof()
1524 txd = &sc->sc_txdescs[idx]; in vge_encap()
1689 sc->sc_txdescs[pidx].td_frag[0].tf_buflen |= in vge_start()
1763 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); in vge_init()
1765 VGE_CDTXOFF(0), sizeof(sc->sc_txdescs), in vge_init()
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| D | if_sip.c | 243 #define sc_txdescs sc_control_data->scd_txdescs macro
536 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); in sip_init_txring()
538 sipd = &sc->sc_txdescs[i]; in sip_init_txring()
560 struct sip_desc *sipd = &sc->sc_txdescs[x]; in sip_init_txdesc()
1497 sc->sc_txdescs[lasttx].sipd_words[sc->sc_extsts_idx] |= in sipcom_set_extsts()
1527 sc->sc_txdescs[sc->sc_txnext].sipd_words[sc->sc_extsts_idx] |= extsts; in sipcom_set_extsts()
1689 sc->sc_txdescs[lasttx].sipd_words[sc->sc_cmdsts_idx] |= in sipcom_start()
1705 sc->sc_txdescs[sc->sc_txnext].sipd_words[sc->sc_cmdsts_idx] |= in sipcom_start()
2052 cmdsts = le32toh(sc->sc_txdescs[ in sipcom_txintr()
2907 (sc->sc_txdescs[ in sipcom_stop()
[all …]
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| D | if_casvar.h | 195 #define sc_txdescs sc_control_data->ccd_txdescs macro
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| D | if_cas.c | 1082 sc->sc_txdescs[i].cd_flags = 0; in cas_meminit()
1083 sc->sc_txdescs[i].cd_addr = 0; in cas_meminit()
2085 sc->sc_txdescs[frag].cd_addr = in cas_encap()
2090 sc->sc_txdescs[frag].cd_flags = CAS_DMA_WRITE(flags); in cas_encap()
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| /netbsd/src/sys/arch/evbppc/virtex/dev/ |
| D | if_temac.c | 170 #define sc_txdescs sc_control_data->cd_txdesc macro
416 sc->sc_txdescs[i].desc_next = sc->sc_cdaddr + in temac_attach()
418 sc->sc_txdescs[i].desc_stat = CDMAC_STAT_DONE; in temac_attach()
423 sc->sc_txdescs[i].desc_stat = CDMAC_STAT_DONE; in temac_attach()
742 sc->sc_txdescs[sc->sc_txcur].desc_addr = in temac_start()
744 sc->sc_txdescs[sc->sc_txcur].desc_size = in temac_start()
746 sc->sc_txdescs[sc->sc_txcur].desc_stat = in temac_start()
768 sc->sc_txdescs[tail].desc_stat |= CDMAC_STAT_STOP | in temac_start()
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| /netbsd/src/sys/arch/powerpc/ibm4xx/dev/ |
| D | if_emac.c | 189 #define sc_txdescs sc_control_data->ecd_txdesc macro
774 &sc->sc_txdescs[nexttx]; in emac_start()
792 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_LAST; in emac_start()
799 sc->sc_txdescs[lasttx].md_stat_ctrl |= MAL_TX_INTERRUPT; in emac_start()
812 sc->sc_txdescs[firsttx].md_stat_ctrl |= MAL_TX_READY; in emac_start()
908 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); in emac_init()
910 sc->sc_txdescs[EMAC_NTXDESC - 1].md_stat_ctrl |= MAL_TX_WRAP; in emac_init()
1278 txstat = sc->sc_txdescs[txs->txs_lastdesc].md_stat_ctrl; in emac_txreap()
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| /netbsd/src/sys/dev/ic/ |
| D | atw.c | 1265 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); in atw_init()
1267 sc->sc_txdescs[i].at_ctl = 0; in atw_init()
1269 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */; in atw_init()
1270 sc->sc_txdescs[i].at_buf2 = in atw_init()
1274 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER); in atw_init()
3304 le32toh(sc->sc_txdescs[i].at_stat)); in atw_txintr()
3306 le32toh(sc->sc_txdescs[i].at_flags)); in atw_txintr()
3308 le32toh(sc->sc_txdescs[i].at_buf1)); in atw_txintr()
3310 le32toh(sc->sc_txdescs[i].at_buf2)); in atw_txintr()
3319 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat); in atw_txintr()
[all …]
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| D | gem.c | 951 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); in gem_meminit()
953 sc->sc_txdescs[i].gd_flags = 0; in gem_meminit()
954 sc->sc_txdescs[i].gd_addr = 0; in gem_meminit()
1354 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); in gem_txsoft_print()
1356 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); in gem_txsoft_print()
1539 sc->sc_txdescs[nexttx].gd_addr = in gem_start()
1545 sc->sc_txdescs[nexttx].gd_flags = in gem_start()
1553 sc->sc_txdescs[lasttx].gd_flags = in gem_start()
1556 sc->sc_txdescs[nexttx].gd_addr = in gem_start()
1565 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); in gem_start()
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| D | elinkxlvar.h | 56 struct ex_txdesc sc_txdescs[EX_NDPD]; member
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| D | elinkxl.c | 1644 sc->sc_txdescs[i].tx_dmamap = sc->sc_tx_dmamaps[i]; in ex_init_txdescs()
1645 sc->sc_txdescs[i].tx_dpd = &sc->sc_dpd[i]; in ex_init_txdescs()
1647 sc->sc_txdescs[i].tx_next = &sc->sc_txdescs[i + 1]; in ex_init_txdescs()
1649 sc->sc_txdescs[i].tx_next = NULL; in ex_init_txdescs()
1651 sc->tx_free = &sc->sc_txdescs[0]; in ex_init_txdescs()
1652 sc->tx_ftail = &sc->sc_txdescs[EX_NDPD-1]; in ex_init_txdescs()
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| D | tulip.c | 808 txd = &sc->sc_txdescs[nexttx]; in tlp_start()
824 sc->sc_txdescs[sc->sc_txnext].td_ctl |= htole32(TDCTL_Tx_FS); in tlp_start()
825 sc->sc_txdescs[lasttx].td_ctl |= htole32(TDCTL_Tx_LS); in tlp_start()
831 txd = &sc->sc_txdescs[seg]; in tlp_start()
883 sc->sc_txdescs[lasttx].td_ctl |= htole32(TDCTL_Tx_IC); in tlp_start()
894 sc->sc_txdescs[last_txs->txs_firstdesc].td_ctl |= in tlp_start()
904 sc->sc_txdescs[firsttx].td_status |= htole32(TDSTAT_OWN); in tlp_start()
1424 txd = &sc->sc_txdescs[i]; in tlp_txintr()
1433 le32toh(sc->sc_txdescs[i].td_bufaddr2)); in tlp_txintr()
1440 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].td_status); in tlp_txintr()
[all …]
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| D | aic6915var.h | 139 #define sc_txdescs sc_control_data->scd_txdescs macro
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| D | aic6915.c | 388 txd = &sc->sc_txdescs[producer]; in sf_start()
479 sc->sc_txdescs[last].td_word0 |= TD_W0_INTR; in sf_start()
940 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); in sf_init()
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| D | gemvar.h | 193 #define sc_txdescs sc_control_data->gcd_txdescs macro
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| D | tulipvar.h | 426 #define sc_txdescs sc_control_data->tcd_txdescs macro
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| D | atwvar.h | 222 #define sc_txdescs sc_control_data->acd_txdescs macro
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