Searched refs:AVX2 (Results 1 – 22 of 22) sorted by relevance
| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86Subtarget.h | 54 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512 enumerator
208 bool hasAVX2() const { return X86SSELevel >= AVX2; } in hasAVX2()
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| D | X86.td | 113 def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
114 "Enable AVX2 instructions",
606 // Gather is available since Haswell (AVX2 set). So technically, we can
607 // generate Gathers on all AVX2 processors. But the overhead on HSW is high.
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| D | X86InstrFormats.td | 785 // AVX2 Instruction Templates:
786 // Instructions introduced in AVX2 (no SSE equivalent forms)
788 // AVX28I - AVX2 instructions with T8PD prefix.
789 // AVX2AIi8 - AVX2 instructions with TAPD prefix and ImmT = Imm8.
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| D | X86CallingConv.td | 232 // since the boolean types in AVX/AVX2 are promoted by default.
558 // since the boolean types in AVX/AVX2 are promoted by default.
873 // since the boolean types in AVX/AVX2 are promoted by default.
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| D | X86Schedule.td | 494 // AVX2.
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| D | X86SchedSandyBridge.td | 587 // AVX2/FMA is not supported on that architecture, but we should define the basic
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| D | X86InstrSSE.td | 542 // have AVX2. Execution domain fixing will convert to integer if AVX2 is
5049 // AVX2 Patterns
5096 // AVX2 Register-Memory patterns
7067 // AVX2 adds register forms
7519 // AVX2 Instructions
7522 /// AVX2_blend_rmi - AVX2 blend with 8-bit immediate
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| D | X86SchedSkylakeClient.td | 596 // AVX2.
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| D | X86ScheduleZnver3.td | 1331 // AVX2.
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| D | X86ScheduleZnver4.td | 1373 // AVX2.
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| D | X86SchedSkylakeServer.td | 592 // AVX2.
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| D | X86SchedIceLake.td | 600 // AVX2.
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| /openbsd/src/gnu/llvm/clang/lib/Basic/Targets/ |
| D | X86.cpp | 366 .Case("+avx2", AVX2) in handleTargetFeatures()
833 case AVX2: in getTargetDefines()
866 case AVX2: in getTargetDefines()
1025 .Case("avx2", SSELevel >= AVX2) in hasFeature()
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| D | X86.h | 64 AVX2, enumerator
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| /openbsd/src/gnu/llvm/llvm/lib/Analysis/ |
| D | VFABIDemangling.cpp | 38 .Case("d", VFISAKind::AVX2) in tryParseISA()
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| /openbsd/src/gnu/llvm/llvm/include/llvm/Analysis/ |
| D | VectorUtils.h | 49 AVX2, // x86 AVX2 enumerator
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| /openbsd/src/gnu/llvm/llvm/docs/ |
| D | TestingGuide.rst | 458 of a specific sub-architecture, for example only to Intel chips that support ``AVX2``.
467 ; RUN: llc -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX2
477 ; AVX2: @test1
478 ; AVX2: vpsubusw LCPI0_0(%rip), %xmm0, %xmm0
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| D | LangRef.rst | 2290 <isa>:= b | c | d | e -> X86 SSE, AVX, AVX2, AVX512
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| /openbsd/src/gnu/llvm/llvm/ |
| D | CREDITS.TXT | 508 D: X86 codegen and disassembler improvements. AVX2 support.
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| /openbsd/src/gnu/llvm/clang/include/clang/Basic/ |
| D | BuiltinsX86.def | 537 // AVX2
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| /openbsd/src/gnu/llvm/llvm/include/llvm/IR/ |
| D | IntrinsicsX86.td | 1410 // AVX2
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| /openbsd/src/gnu/llvm/clang/docs/ |
| D | UsersManual.rst | 3784 - ``-march=x86-64-v3``: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE
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