| /openbsd/src/usr.bin/file/magdir/ |
| D | games | 19 >4 long 0x26 II Map file (BSP)
20 >4 long 0x2E III Map file (BSP)
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| /openbsd/src/sys/dev/pci/drm/radeon/ |
| D | sumod.h | 302 # define BSP(x) ((x) << 0) macro
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| D | rv770d.h | 234 # define BSP(x) ((x) << 0) macro
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| D | sumo_dpm.c | 327 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); in sumo_calculate_bsp()
328 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); in sumo_calculate_bsp()
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| D | sid.h | 279 # define BSP(x) ((x) << 0) macro
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| D | rv770_dpm.c | 834 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); in rv770_setup_bsp()
835 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); in rv770_setup_bsp()
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| D | r600_dpm.c | 338 WREG32(CG_BSP, BSP(p) | BSU(u)); in r600_set_bsp()
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| D | r600d.h | 1436 # define BSP(x) ((x) << 0) macro
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| D | si_dpm.c | 3693 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); in si_setup_bsp()
3694 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); in si_setup_bsp()
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| /openbsd/src/gnu/usr.bin/binutils-2.17/opcodes/ |
| D | ia64-ic.tbl | 71 mov-from-AR-BSP; IC:mov-from-AR-M[Field(ar3) == BSP]
138 mov-to-AR-BSP; IC:mov-to-AR-M[Field(ar3) == BSP]
242 rse-readers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, IC:mov-from-AR-BSP, I…
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| D | ia64-raw.tbl | 3 AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ia, br…
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| D | ia64-waw.tbl | 3 AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ret, c…
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| /openbsd/src/gnu/usr.bin/binutils/opcodes/ |
| D | ia64-ic.tbl | 71 mov-from-AR-BSP; IC:mov-from-AR-M[Field(ar3) == BSP]
137 mov-to-AR-BSP; IC:mov-to-AR-M[Field(ar3) == BSP]
239 rse-readers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, IC:mov-from-AR-BSP, I…
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| D | ia64-raw.tbl | 3 AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ia, br…
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| D | ia64-waw.tbl | 3 AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ret, c…
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.h | 194 BSP, enumerator
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| D | AArch64SchedFalkorDetails.td | 914 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^(BIF|BIT|BSL|BSP)v8i8$")>;
938 def : InstRW<[FalkorWr_2VXVY_1cyc], (instregex "^(BIF|BIT|BSL|BSP)v16i8$")>;
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| D | AArch64SchedCyclone.td | 502 // BIF,BIT,BSL,BSP
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| D | AArch64SchedExynosM3.td | 668 def : InstRW<[M3WriteNALU1], (instregex "^(BIF|BIT|BSL|BSP)v")>;
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| D | AArch64SchedA57.td | 527 def : InstRW<[A57Write_3cyc_2V], (instregex "^(BIF|BIT|BSL|BSP)v16i8")>;
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| D | AArch64SchedExynosM5.td | 849 def : InstRW<[M5WriteNALU2], (instregex "^(BIF|BIT|BSL|BSP)v")>;
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| D | AArch64SchedExynosM4.td | 811 def : InstRW<[M4WriteNALU1], (instregex "^(BIF|BIT|BSL|BSP)v")>;
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| D | AArch64ISelLowering.cpp | 2377 MAKE_CASE(AArch64ISD::BSP) in getTargetNodeName()
8594 SDValue BSP = in LowerFCOPYSIGN() local
8595 DAG.getNode(AArch64ISD::BSP, DL, VecVT, SignMaskV, VecVal1, VecVal2); in LowerFCOPYSIGN()
8597 return DAG.getTargetExtractSubreg(AArch64::hsub, DL, VT, BSP); in LowerFCOPYSIGN()
8599 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, BSP); in LowerFCOPYSIGN()
8601 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, BSP); in LowerFCOPYSIGN()
8603 return BitCast(VT, BSP, DAG); in LowerFCOPYSIGN()
16075 return DAG.getNode(AArch64ISD::BSP, DL, VT, Sub, SubSibling, AddSibling); in tryCombineToBSL()
16103 return DAG.getNode(AArch64ISD::BSP, DL, VT, SDValue(BVN0, 0), in tryCombineToBSL()
21516 case AArch64ISD::BSP: in PerformDAGCombine()
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| D | AArch64InstrInfo.td | 677 def AArch64bsp: SDNode<"AArch64ISD::BSP", SDT_AArch64trivec>;
4844 // Pseudo bitwise select pattern BSP.
4846 defm BSP : SIMDLogicalThreeVectorPseudo<TriOpFrag<(or (and node:$LHS, node:$MHS),
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| /openbsd/src/sys/dev/pci/drm/amd/amdgpu/ |
| D | sid.h | 280 # define BSP(x) ((x) << 0) macro
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