Home
last modified time | relevance | path

Searched refs:CPSR (Results 1 – 25 of 45) sorted by relevance

12

/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DMVETailPredUtils.h122 MIB.addReg(ARM::CPSR, RegState::Define);
130 MIB.addReg(ARM::CPSR);
158 MIB.addReg(ARM::CPSR);
186 MIB.addReg(ARM::CPSR);
DThumb2SizeReduction.cpp256 return is_contained(MCID.implicit_defs(), ARM::CPSR); in HasImplicitCPSRDef()
302 if (Reg == 0 || Reg == ARM::CPSR) in canAddPseudoFlagDep()
382 if (Reg == 0 || Reg == ARM::CPSR) in VerifyLowRegs()
655 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) in ReduceSpecial()
816 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceTo2Addr()
880 if (!Reg || Reg == ARM::CPSR) in ReduceToNarrow()
907 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceToNarrow()
959 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR) in ReduceToNarrow()
984 if (MO.getReg() != ARM::CPSR) in UpdateCPSRDef()
999 if (MO.getReg() != ARM::CPSR) in UpdateCPSRUse()
[all …]
DARMInstrThumb.td415 // tADDrSPi, but we may need to insert a sequence that clobbers CPSR.
419 let Defs = [CPSR];
968 let isCommutable = 1, Uses = [CPSR] in
1001 /// instruction modifies the CPSR register.
1004 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
1005 let hasPostISelHook = 1, Defs = [CPSR] in {
1006 let isCommutable = 1, Uses = [CPSR] in
1009 [(set tGPR:$Rdn, CPSR, (ARMadde tGPR:$Rn, tGPR:$Rm,
1010 CPSR))]>,
1016 [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rm,
[all …]
DThumb1InstrInfo.cpp60 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I) in copyPhysReg()
64 ->addRegisterDead(ARM::CPSR, RegInfo); in copyPhysReg()
DARMFastISel.cpp233 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
245 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { in DefinesOptionalPredicate() argument
252 if (MO.getReg() == ARM::CPSR) in DefinesOptionalPredicate()
253 *CPSR = true; in DefinesOptionalPredicate()
290 bool CPSR = false; in AddOptionalDefs() local
291 if (DefinesOptionalPredicate(MI, &CPSR)) in AddOptionalDefs()
292 MIB.add(CPSR ? t1CondCodeOp() : condCodeOp()); in AddOptionalDefs()
1254 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); in SelectBranch()
1277 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); in SelectBranch()
1315 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); in SelectBranch()
[all …]
DARMBaseInstrInfo.cpp625 MI.getOperand(1).getReg() != ARM::CPSR) && in PredicateInstruction()
666 bool ClobbersCPSR = MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR); in ClobbersPredicate()
667 bool IsCPSR = MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR; in ClobbersPredicate()
687 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead()) in isCPSRDefined()
765 if (MO.getReg() != ARM::CPSR) in IsCPSRDead()
844 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
864 .addReg(ARM::CPSR, RegState::Implicit | RegState::Define); in copyToCPSR()
984 } else if (SrcReg == ARM::CPSR) { in copyPhysReg()
987 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
2280 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
[all …]
DARMInstrInfo.td85 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
1673 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1674 let hasPostISelHook = 1, Defs = [CPSR] in {
1680 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1685 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1692 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1699 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1707 let hasPostISelHook = 1, Defs = [CPSR] in {
1712 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1718 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
[all …]
DARMInstrThumb2.td726 /// changed to modify CPSR.
865 /// instruction modifies the CPSR register.
868 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
869 let hasPostISelHook = 1, Defs = [CPSR] in {
877 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
883 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
892 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
900 let hasPostISelHook = 1, Defs = [CPSR] in {
906 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
913 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
[all …]
DARM.td390 /// Some instructions update CPSR partially, which can add false dependency for
392 /// mapped to a separate physical register. Avoid partial CPSR update for these
395 /// that partially update CPSR and add false dependency on the previous
396 /// CPSR setting instruction.
399 "Avoid CPSR partial update for OOO execution">;
401 /// Disable +1 predication cost for instructions updating CPSR.
403 /// True if disable +1 predication cost for instructions updating CPSR. Enabled for Cortex-A57.
407 "Disable +1 predication cost for instructions updating CPSR">;
DThumb2ITBlockPass.cpp173 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR) in MoveCopyOutOfITBlock()
DARMInstructionSelector.cpp602 .add(predOps(Cond, ARM::CPSR)); in insertComparison()
796 .add(predOps(ARMCC::EQ, ARM::CPSR)); in selectSelect()
1136 .add(predOps(ARMCC::NE, ARM::CPSR)); in select()
DARMExpandPseudoInsts.cpp1119 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit); in CMSEClearGPRegs()
1243 .addReg(ARM::CPSR, RegState::Kill); in CMSEClearFPRegsV8()
1784 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1808 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1901 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1907 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1929 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
2264 .addReg(ARM::CPSR, RegState::Define) in ExpandMI()
2466 .addReg(ARM::CPSR, RegState::Define); in ExpandMI()
2665 .addReg(ARM::CPSR, RegState::Undef); in ExpandMI()
DARMAsmPrinter.cpp1773 .addReg(ARM::CPSR) in emitInstruction()
1829 .addReg(ARM::CPSR) in emitInstruction()
1960 .addReg(ARM::CPSR) in emitInstruction()
1979 .addReg(ARM::CPSR) in emitInstruction()
1994 .addReg(ARM::CPSR) in emitInstruction()
DMVETPAndVPTOptimisationsPass.cpp200 MIB.addReg(ARM::CPSR, RegState::Define); in RevertWhileLoopSetup()
209 MIB.addReg(ARM::CPSR); in RevertWhileLoopSetup()
DARMLowOverheadLoops.cpp1460 RDA->isSafeToDefRegAt(MI, MCRegister::from(ARM::CPSR), Ignore); in RevertLoopDec()
1490 MIB.addReg(ARM::CPSR); in RevertLoopEndDec()
1501 MIB.addReg(ARM::CPSR); in RevertLoopEndDec()
DREADME-Thumb.txt226 to toggle the 's' bit since they do not set CPSR when they are inside IT blocks.
DARMISelLowering.cpp4817 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR, in getARMCmp()
4974 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSignedALUO()
5119 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT()
5518 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC()
5553 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC()
5660 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond()
5709 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBRCOND()
5763 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
5772 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
5789 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
[all …]
DThumb1FrameLowering.cpp463 .addDef(ARM::CPSR) in emitPrologue()
469 .addDef(ARM::CPSR) in emitPrologue()
DARMRegisterInfo.td184 def CPSR : ARMReg<0, "cpsr">;
394 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
DARMBaseInstrInfo.h558 return MachineOperand::CreateReg(ARM::CPSR,
/openbsd/src/gnu/usr.bin/binutils/gdb/
Dsparc-stub.c119 Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR }; enumerator
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCTargetDesc.cpp180 if (MO.isReg() && MO.getReg() == ARM::CPSR && in isCPSRDefined()
246 {codeview::RegisterId::ARM_CPSR, ARM::CPSR}, in initLLVMToCVRegMapping()
/openbsd/src/gnu/llvm/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td66 def CPSR : SparcCtrlReg<0, "CPSR">; // Co-processor state register.
/openbsd/src/gnu/llvm/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp1132 case Sparc::CPSR: in parseSparcAsmOperand()
1275 RegNo = Sparc::CPSR; in matchRegisterName()
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp2486 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
7190 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, in ParseInstruction()
10032 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
10082 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
10089 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
10135 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
10143 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
10341 Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) || in processInstruction()
10509 Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
10530 Inst.getOperand(4).getReg() == ARM::CPSR && in processInstruction()
[all …]

12