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Searched refs:CSR_READ_4 (Results 1 – 25 of 58) sorted by relevance

123

/openbsd/src/sys/dev/mii/
Ddcphy.c69 CSR_READ_4(sc, reg) | x)
73 CSR_READ_4(sc, reg) & ~x)
211 mode = CSR_READ_4(dc_sc, DC_NETCFG); in dcphy_service()
273 reg = CSR_READ_4(dc_sc, DC_10BTSTAT); in dcphy_service()
319 reg = CSR_READ_4(dc_sc, DC_10BTSTAT); in dcphy_status()
323 if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) { in dcphy_status()
325 tstat = CSR_READ_4(dc_sc, DC_10BTSTAT); in dcphy_status()
377 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL) in dcphy_status()
382 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX) in dcphy_status()
412 if ((CSR_READ_4(sc, DC_10BTSTAT) & DC_TSTAT_ANEGSTAT) in dcphy_mii_phy_auto()
/openbsd/src/sys/dev/pci/
Dif_alc.c202 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_813x()
231 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_816x()
271 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_813x()
297 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_816x()
342 reg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_miibus_statchg()
385 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_readreg()
416 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_writereg()
554 opt = CSR_READ_4(sc, ALC_OPT_CFG); in alc_get_macaddr_813x()
555 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && in alc_get_macaddr_813x()
556 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { in alc_get_macaddr_813x()
[all …]
Dif_sis.c150 CSR_READ_4(sc, reg) | (x))
154 CSR_READ_4(sc, reg) & ~(x))
157 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
160 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
189 CSR_READ_4(sc, SIS_CSR); in sis_delay()
272 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) in sis_eeprom_getword()
331 rxfilt = CSR_READ_4(sc, SIS_RXFILT_CTL); in sis_read_mac()
332 csrsave = CSR_READ_4(sc, SIS_CSR); in sis_read_mac()
340 enaddr[0] = letoh16(CSR_READ_4(sc, SIS_RXFILT_DATA) & 0xffff); in sis_read_mac()
342 enaddr[1] = letoh16(CSR_READ_4(sc, SIS_RXFILT_DATA) & 0xffff); in sis_read_mac()
[all …]
Dif_nge.c182 CSR_READ_4(sc, reg) | (x))
186 CSR_READ_4(sc, reg) & ~(x))
189 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
192 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
200 CSR_READ_4(sc, NGE_CSR); in nge_delay()
284 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) in nge_eeprom_getword()
403 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; in nge_mii_readreg()
425 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) in nge_mii_readreg()
535 txcfg = CSR_READ_4(sc, NGE_TX_CFG); in nge_miibus_statchg()
536 rxcfg = CSR_READ_4(sc, NGE_RX_CFG); in nge_miibus_statchg()
[all …]
Dif_bge.c874 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) in bge_nvram_getbyte()
882 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); in bge_nvram_getbyte()
889 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { in bge_nvram_getbyte()
901 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); in bge_nvram_getbyte()
910 CSR_READ_4(sc, BGE_NVRAM_SWARB); in bge_nvram_getbyte()
967 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) in bge_eeprom_getbyte()
977 byte = CSR_READ_4(sc, BGE_EE_DATA); in bge_eeprom_getbyte()
1014 autopoll = CSR_READ_4(sc, BGE_MI_MODE); in bge_miibus_readreg()
1023 CSR_READ_4(sc, BGE_MI_COMM); /* force write */ in bge_miibus_readreg()
1027 val = CSR_READ_4(sc, BGE_MI_COMM); in bge_miibus_readreg()
[all …]
Dif_ale.c146 v = CSR_READ_4(sc, ALE_MDIO); in ale_miibus_readreg()
175 v = CSR_READ_4(sc, ALE_MDIO); in ale_miibus_writereg()
222 reg = CSR_READ_4(sc, ALE_MAC_CFG); in ale_miibus_statchg()
273 reg = CSR_READ_4(sc, ALE_SPI_CTRL); in ale_get_macaddr()
285 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | in ale_get_macaddr()
289 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); in ale_get_macaddr()
302 ea[0] = CSR_READ_4(sc, ALE_PAR0); in ale_get_macaddr()
303 ea[1] = CSR_READ_4(sc, ALE_PAR1); in ale_get_macaddr()
422 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { in ale_attach()
455 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> in ale_attach()
[all …]
Dif_age.c188 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> in age_attach()
199 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), in age_attach()
200 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); in age_attach()
316 v = CSR_READ_4(sc, AGE_MDIO); in age_miibus_readreg()
349 v = CSR_READ_4(sc, AGE_MDIO); in age_miibus_writereg()
395 reg = CSR_READ_4(sc, AGE_MAC_CFG); in age_miibus_statchg()
397 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | in age_miibus_statchg()
447 status = CSR_READ_4(sc, AGE_INTR_STATUS); in age_intr()
513 reg = CSR_READ_4(sc, AGE_SPI_CTRL); in age_get_macaddr()
526 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | in age_get_macaddr()
[all …]
Dif_jme.c155 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) in jme_miibus_readreg()
186 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) in jme_miibus_writereg()
368 reg = CSR_READ_4(sc, JME_SMBCSR); in jme_eeprom_read_byte()
383 reg = CSR_READ_4(sc, JME_SMBINTF); in jme_eeprom_read_byte()
393 reg = CSR_READ_4(sc, JME_SMBINTF); in jme_eeprom_read_byte()
449 par0 = CSR_READ_4(sc, JME_PAR0); in jme_reg_macaddr()
450 par1 = CSR_READ_4(sc, JME_PAR1); in jme_reg_macaddr()
591 reg = CSR_READ_4(sc, JME_CHIPMODE); in jme_attach()
614 reg = CSR_READ_4(sc, JME_SMBCSR); in jme_attach()
633 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & in jme_attach()
[all …]
Dif_lge.c161 CSR_READ_4(sc, reg) | (x))
165 CSR_READ_4(sc, reg) & ~(x))
168 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
171 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
186 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) in lge_eeprom_getword()
194 val = CSR_READ_4(sc, LGE_EEDATA); in lge_eeprom_getword()
239 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) in lge_miibus_readreg()
247 return (CSR_READ_4(sc, LGE_GMIICTL) >> 16); in lge_miibus_readreg()
260 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) in lge_miibus_writereg()
352 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) in lge_reset()
[all …]
Dif_vgevar.h106 #define CSR_READ_4(sc, reg) \ macro
118 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
125 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
Dif_wb.c164 CSR_READ_4(sc, reg) | x)
168 CSR_READ_4(sc, reg) & ~x)
172 CSR_READ_4(sc, WB_SIO) | x)
176 CSR_READ_4(sc, WB_SIO) & ~x)
232 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) in wb_eeprom_getword()
356 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; in wb_mii_readreg()
382 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) in wb_mii_readreg()
508 rxfilt = CSR_READ_4(sc, WB_NETCFG); in wb_setmulti()
559 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { in wb_setcfg()
565 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && in wb_setcfg()
[all …]
Dif_bwi_pci.c119 for (i = 0; CSR_READ_4(sc, BWI_RESET_STATUS) && i < 30; i++) in bwi_reset_bcm4331()
123 CSR_READ_4(sc, BWI_RESET_CTRL); in bwi_reset_bcm4331()
126 CSR_READ_4(sc, BWI_RESET_CTRL); in bwi_reset_bcm4331()
Dif_stge.c283 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) in stge_attach()
437 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) in stge_dma_wait()
755 txstat = CSR_READ_4(sc, STGE_TxStatus); in stge_intr()
1024 (void) CSR_READ_4(sc, STGE_OctetRcvOk); in stge_stats_update()
1029 (void) CSR_READ_4(sc, STGE_OctetXmtdOk); in stge_stats_update()
1032 CSR_READ_4(sc, STGE_LateCollisions) + in stge_stats_update()
1033 CSR_READ_4(sc, STGE_MultiColFrames) + in stge_stats_update()
1034 CSR_READ_4(sc, STGE_SingleColFrames); in stge_stats_update()
1052 ac = CSR_READ_4(sc, STGE_AsicCtrl); in stge_reset()
1068 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) in stge_reset()
Dif_iwi.c125 return CSR_READ_4(sc, IWI_CSR_INDIRECT_DATA); in MEM_READ_4()
667 val = CSR_READ_4(sc, IWI_CSR_CURRENT_TX_RATE); in iwi_media_status()
1087 hw = CSR_READ_4(sc, IWI_CSR_RX_RIDX); in iwi_rx_intr()
1130 hw = CSR_READ_4(sc, txq->csr_ridx); in iwi_tx_intr()
1157 if ((r = CSR_READ_4(sc, IWI_CSR_INTR)) == 0 || r == 0xffffffff) in iwi_intr()
1477 (CSR_READ_4(sc, IWI_CSR_IO) & IWI_IO_RADIO_ENABLED) ? in iwi_ioctl()
1508 if (CSR_READ_4(sc, IWI_CSR_RST) & IWI_RST_MASTER_DISABLED) in iwi_stop_master()
1517 tmp = CSR_READ_4(sc, IWI_CSR_RST); in iwi_stop_master()
1530 tmp = CSR_READ_4(sc, IWI_CSR_CTL); in iwi_reset()
1537 if (CSR_READ_4(sc, IWI_CSR_CTL) & IWI_CTL_CLOCK_READY) in iwi_reset()
[all …]
Dif_ipw.c120 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA); in MEM_READ_4()
933 r = CSR_READ_4(sc, IPW_CSR_RX_READ_INDEX); in ipw_rx_intr()
1026 r = CSR_READ_4(sc, IPW_CSR_TX_READ_INDEX); in ipw_tx_intr()
1050 if ((r = CSR_READ_4(sc, IPW_CSR_INTR)) == 0 || r == 0xffffffff) in ipw_intr()
1381 (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED) ? in ipw_ioctl()
1449 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) in ipw_stop_master()
1457 tmp = CSR_READ_4(sc, IPW_CSR_RST); in ipw_stop_master()
1470 tmp = CSR_READ_4(sc, IPW_CSR_CTL); in ipw_reset()
1475 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) in ipw_reset()
1482 tmp = CSR_READ_4(sc, IPW_CSR_RST); in ipw_reset()
[all …]
Dif_tlreg.h507 #define CSR_READ_4(sc, reg) \ macro
516 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) | (x))
518 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) & ~(x))
Dif_et.c325 val = CSR_READ_4(sc, ET_MII_IND); in et_miibus_readreg()
339 val = CSR_READ_4(sc, ET_MII_STAT); in et_miibus_readreg()
368 val = CSR_READ_4(sc, ET_MII_IND); in et_miibus_writereg()
392 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); in et_miibus_statchg()
398 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); in et_miibus_statchg()
922 intrs = CSR_READ_4(sc, ET_INTR_STATUS); in et_intr()
1115 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { in et_stop_rxdma()
1189 pktfilt = CSR_READ_4(sc, ET_PKTFILT); in et_setmulti()
1190 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); in et_setmulti()
1610 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { in et_start_rxdma()
[all …]
Dif_tl.c309 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); in tl_dio_read32()
892 cmd = CSR_READ_4(sc, TL_HOSTCMD); in tl_softreset()
1187 cmd = CSR_READ_4(sc, TL_HOSTCMD); in tl_intvec_txeoc()
1206 (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); in tl_intvec_adchk()
1320 *p++ = CSR_READ_4(sc, TL_DIO_DATA); in tl_stats_update()
1321 *p++ = CSR_READ_4(sc, TL_DIO_DATA); in tl_stats_update()
1322 *p++ = CSR_READ_4(sc, TL_DIO_DATA); in tl_stats_update()
1323 *p++ = CSR_READ_4(sc, TL_DIO_DATA); in tl_stats_update()
1324 *p++ = CSR_READ_4(sc, TL_DIO_DATA); in tl_stats_update()
1516 cmd = CSR_READ_4(sc, TL_HOSTCMD); in tl_start()
Dif_se.c193 #define CSR_READ_4(sc, reg) \ macro
215 val = CSR_READ_4(sc, ROMInterface); in se_read_eeprom()
324 val = CSR_READ_4(sc, GMIIControl); in se_miibus_cmd()
418 ctl = CSR_READ_4(sc, StationControl); in se_miibus_statchg()
491 CSR_READ_4(sc, IntrControl); in se_reset()
1050 status = CSR_READ_4(sc, IntrStatus); in se_intr()
1072 status = CSR_READ_4(sc, IntrStatus); in se_intr()
1417 CSR_READ_4(sc, IntrMask); in se_stop()
/openbsd/src/sys/dev/ic/
Dmtd8xxreg.h208 #define CSR_READ_4(reg) bus_space_read_4(sc->sc_bust, sc->sc_bush, reg) macro
212 #define CSR_SETBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) | (val))
213 #define CSR_CLRBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) & ~(val))
Ddc.c196 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
199 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
210 CSR_READ_4(sc, DC_BUSCTL); in dc_delay()
246 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { in dc_eeprom_width()
359 r = CSR_READ_4(sc, DC_SIO); in dc_eeprom_getword_pnic()
379 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff; in dc_eeprom_getword_xircom()
382 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; in dc_eeprom_getword_xircom()
420 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) in dc_eeprom_getword()
485 CSR_READ_4(sc, DC_SIO); in dc_mii_readbit()
488 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) in dc_mii_readbit()
[all …]
Dmtd8xx.c152 enaddr[0] = letoh32(CSR_READ_4(MTD_PAR0)); in mtd_attach()
153 enaddr[1] = letoh32(CSR_READ_4(MTD_PAR4)); in mtd_attach()
219 miir = (CSR_READ_4(MTD_MIIMGT) & ~MIIMGT_MASK) | MIIMGT_WRITE | in mtd_mii_command()
262 miir = CSR_READ_4(MTD_MIIMGT); in mtd_miibus_readreg()
324 rxfilt = CSR_READ_4(MTD_TCRRCR) & ~RCR_AM; in mtd_setmulti()
555 if (!(CSR_READ_4(MTD_BCR) & BCR_SWR)) { in mtd_reset()
816 if (CSR_READ_4(MTD_ISR) & ISR_INTRS) in mtd_intr()
824 while((status = CSR_READ_4(MTD_ISR)) & ISR_INTRS) { in mtd_intr()
1020 if (CSR_READ_4(MTD_TCRRCR) & TCR_ENHANCED) in mtd_txeof()
1021 ifp->if_collisions += TSR_NCR_GET(CSR_READ_4(MTD_TSR)); in mtd_txeof()
Dti.c196 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN; in ti_eeprom_putbyte()
220 sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); in ti_eeprom_getbyte()
229 sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); in ti_eeprom_getbyte()
237 sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); in ti_eeprom_getbyte()
248 sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL)); in ti_eeprom_getbyte()
259 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN) in ti_eeprom_getbyte()
993 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR); in ti_iff()
1035 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) { in ti_64bitslot_war()
1039 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) { in ti_64bitslot_war()
1070 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) { in ti_chipinit()
[all …]
Dbwi.c586 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); in bwi_intr()
590 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); in bwi_intr()
611 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; in bwi_intr()
652 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) in bwi_intr()
998 return (CSR_READ_4(sc, BWI_MOBJ_DATA)); in bwi_memobj_read_4()
1046 CSR_READ_4(mac->mac_sc, BWI_STATE_HI); /* dummy read */ in bwi_mac_lateattach()
1266 state_lo = CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_reset()
1272 CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_reset()
1278 CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_reset()
1283 status = CSR_READ_4(sc, BWI_MAC_STATUS); in bwi_mac_reset()
[all …]
Dbwivar.h74 #define CSR_READ_4(sc, reg) \ macro
85 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
90 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
95 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))

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